E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

Download PDF
ID 683578
Date 3/06/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About E-tile Hard IP Design Examples 2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example 3. E-tile CPRI PHY Intel® FPGA IP Design Example 4. E-Tile Dynamic Reconfiguration Design Example 5. E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide Archives
2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example x
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide 2.2. 10GE/25GE with Optional RS-FEC Design Examples 2.3. 100GE with Optional RS-FEC Design Example 2.4. Ethernet Toolkit Overview 2.5. Document Revision History for the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design 2.1.3. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench 2.1.4. Compiling the Compilation-Only Project 2.1.5. Compiling and Configuring the Design Example in Hardware 2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example x
2.1.6.1. 10GE/25GE Design Example 2.1.6.2. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example 2.1.6.3. 100GE PCS Only with Optional (528,514) RS-FEC or (544,514) RS-FEC, and Optional PTP Hardware Design Example
2.2. 10GE/25GE with Optional RS-FEC Design Examples x
2.2.1. Simulation Design Examples 2.2.2. Hardware Design Examples 2.2.3. 10GE/25GE Design Example Interface Signals 2.2.4. 10GE/25GE Design Examples Registers
2.2.1. Simulation Design Examples x
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example 2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.2.2. Hardware Design Examples x
2.2.2.1. 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example Components 2.2.2.2. 10GE/25GE PCS Only with Optional RS-FEC Hardware Design Example Components 2.2.2.3. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example
2.3. 100GE with Optional RS-FEC Design Example x
2.3.1. Simulation Design Examples 2.3.2. Hardware Design Examples 2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals 2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals 2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers 2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1. Simulation Design Examples x
2.3.1.1. Non-PTP E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.3.1.2. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example 2.3.1.3. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE PCS Only with Optional RS-FEC Simulation Design Example 2.3.1.4. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE OTN with Optional RS-FEC Simulation Design Example 2.3.1.5. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2. Hardware Design Examples x
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components 2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example 2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.4. Ethernet Toolkit Overview x
2.4.1. Features
3. E-tile CPRI PHY Intel® FPGA IP Design Example x
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide 3.2. E-tile CPRI PHY Design Example Description 3.3. Document Revision History for the E-tile CPRI PHY Intel® FPGA IP Design Example
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide x
3.1.1. Hardware and Software Requirements 3.1.2. Generating the Design 3.1.3. Directory Structure 3.1.4. Simulating the Design Example Testbench 3.1.5. Compiling the Compilation-Only Project 3.1.6. Compiling and Configuring the Design Example in Hardware 3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
3.2. E-tile CPRI PHY Design Example Description x
3.2.1. Features 3.2.2. Simulation Design Example 3.2.3. Hardware Design Example 3.2.4. Interface Signals 3.2.5. Design Example Register Map for Reconfiguration
4. E-Tile Dynamic Reconfiguration Design Example x
4.1. Quick Start Guide 4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples 4.3. CPRI Dynamic Reconfiguration Design Examples 4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example 4.5. 100G Ethernet Dynamic Reconfiguration Design Example 4.6. Document Revision History for the E-tile Dynamic Reconfiguration Design Example
4.1. Quick Start Guide x
4.1.1. Directory Structure 4.1.2. Generating the Design 4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench 4.1.4. Compiling and Configuring the Design Example in Hardware 4.1.5. Testing the E-tile Dynamic Reconfiguration Hardware Design Example
4.1.2. Generating the Design x
4.1.2.1. Design Example Parameters
4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench x
4.1.3.1. Running the Simulation with Default HEX File 4.1.3.2. Running the Simulation with New HEX File 4.1.3.3. Performing the Link Initialization
4.1.5. Testing the E-tile Dynamic Reconfiguration Hardware Design Example x
4.1.5.1. Running the Design Example in Hardware 4.1.5.2. Power Management Setting for Stratix 10 E-Tile TX Transceiver Signal Integrity Development Kit
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples x
4.2.1. Functional Description 4.2.2. Simulation Design Examples 4.2.3. Hardware Design Examples 4.2.4. 10GE/25GE Design Example Interface Signals 4.2.5. 10GE/25GE Design Examples Registers 4.2.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
4.2.1. Functional Description x
4.2.1.1. Clocking Scheme
4.2.2. Simulation Design Examples x
4.2.2.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Simulation Dynamic Reconfiguration Design Example Components 4.2.2.2. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
4.2.3. Hardware Design Examples x
4.2.3.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components 4.2.3.2. 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.3. CPRI Dynamic Reconfiguration Design Examples x
4.3.1. Functional Description 4.3.2. Simulation Design Examples 4.3.3. Hardware Design Examples 4.3.4. CPRI Design Example Interface Signals 4.3.5. CPRI Design Example Registers 4.3.6. Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
4.3.1. Functional Description x
4.3.1.1. Clocking Scheme
4.3.2. Simulation Design Examples x
4.3.2.1. 24G CPRI PHY with RS-FEC Simulation Dynamic Reconfiguration Design Example Components 4.3.2.2. 9.8G CPRI PHY Simulation Dynamic Reconfiguration Design Example Components
4.3.3. Hardware Design Examples x
4.3.3.1. CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example x
4.4.1. Functional Description 4.4.2. Simulation Design Examples 4.4.3. Hardware Design Examples 4.4.4. 25G Ethernet to CPRI Design Example Interface Signals 4.4.5. 25G Ethernet to CPRI Design Examples Registers 4.4.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
4.4.1. Functional Description x
4.4.1.1. Clocking Scheme 4.4.1.2. Reset
4.4.2. Simulation Design Examples x
4.4.2.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Simulation Dynamic Reconfiguration Design Example Components
4.4.3. Hardware Design Examples x
4.4.3.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components
4.5. 100G Ethernet Dynamic Reconfiguration Design Example x
4.5.1. Functional Description 4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example 4.5.3. Simulation Design Examples 4.5.4. 100GE DR Hardware Design Examples 4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals 4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers 4.5.7. Steps to Enable FEC 4.5.8. Steps to Disable FEC
4.5.3. Simulation Design Examples x
4.5.3.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Simulation Design Example
4.5.4. 100GE DR Hardware Design Examples x
4.5.4.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Hardware Design Example Components
1. About E-tile Hard IP Design Examples
2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example
3. E-tile CPRI PHY Intel® FPGA IP Design Example
4. E-Tile Dynamic Reconfiguration Design Example
5. E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide Archives

4.4.2.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Simulation Dynamic Reconfiguration Design Example Components

The simulation block diagram below is generated using the following settings in the IP parameter editor:
  1. 25G Ethernet to CPRI Protocol as DR Protocol.
  2. Under the 25G Ethernet to CPRI Protocol tab:
    1. 25G PTP RS-FEC as Select DR Design.
    2. Stratix 10 E-Tile TX Transceiver Signal Integrity Development Kit as the target development kit.
Figure 40. Simulation Block Diagram for 25G Ethernet to CPRI Dynamic Reconfiguration Design Example

The successful test displays the dynamic reconfiguration transition flow between various modes. Use preset HEX file provided for each design example or modify provided C code to enable specific transition simulation. For more information on HEX file, refer to Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench.

To test a specific transition, reorder the dynamic reconfiguration transition flow tests in the main.c file and regenerate a new HEX file. Each test describes a transition from the starting rate to the destination rate.

This is the default simulation test sequence based on the provided HEX file.
  1. Toggle sl_tx_rst_n and sl_rx_rst_n reset signals.
  2. Link Initialization. For more information, refer to Performing the Link Initialization.
  3. Dynamic reconfiguration (DR) test from 25G PTP with RS-FEC to 24G CPRI with RS-FEC
  4. DR test from 24G CPRI with RS-FEC to 10G CPRI
  5. DR test from 10G CPRI to 9.8G CPRI
  6. DR test from 9.8G CPRI to 4.9G CPRI
  7. DR test from 4.9G CPRI to 2.4G CPRI
  8. DR test from 2.4G CPRI to 24G CPRI with RS-FEC
  9. DR test from 24G CPRI with RS-FEC to 25G PTP with RS-FEC
  10. DR test from 25G PTP with RS-FEC to 10G CPRI
  11. DR test from 10G CPRI to 10G CPRI with tunneling mode
  12. DR test from 10G CPRI with tunneling mode to 10G CPRI
  13. DR test from 10G CPRI to 25G PTP with RS-FEC
  14. DR test from 25G PTP with RS-FEC to 9.8G CPRI
  15. DR test from 9.8G CPRI to 9.8G CPRI with tunneling mode
  16. DR test from 9.8G CPRI with tunneling mode to 9.8G CPRI
  17. DR test from 9.8G CPRI to 25G PTP with RS-FEC
  18. DR test from 25G PTP with RS-FEC to 4.9G CPRI
  19. DR test from 4.9G CPRI to 4.9G CPRI with tunneling mode
  20. DR test from 4.9G CPRI with tunneling mode to 4.9G CPRI
  21. DR test from 4.9G CPRI to 25G PTP with RS-FEC
  22. DR test from 25G PTP with RS-FEC to 2.4G CPRI
  23. DR test from 2.4G CPRI to 2.4G CPRI with tunneling mode
  24. DR test from 2.4G CPRI with tunneling mode to 2.4G CPRI
  25. DR test from 2.4G CPRI to 25G PTP with RS-FEC
  26. DR test from 25G PTP with RS-FEC to 1G PTP
  27. DR test from 1G PTP to 10G PTP
  28. DR test from 10G PTP to 1G PTP
  29. DR test from 1G PTP to 25G PTP with RS-FEC
Each of the dynamic reconfiguration tests follows these steps:
  1. Assert sl_tx_rst_n and sl_rx_rst_n reset signals.
  2. Disable SERDES. Use PMA attribute code 0x0001 in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  3. Perform reference clock mux switching. For more information about the details of the changed register values, refer to the c3_reconfig.c file.
    1. Switch the PMA controller clock to the transceiver refclk1 clock.
    2. Change refclk reference clock from the original speed mode clock to the destination speed mode clock.
      Note: For information on speed mode clocks, refer to 25G Ethernet to CPRI Design Example Interface Signals.
    3. Switch the PMA controller clock to the transceiver refclk0 clock.
    Note: Steps 3a and 3c are only applicable for Ethernet dynamic reconfiguration hardware test to avoid potential hardware glitch due to the reference clock switch operation. These steps are available in the hardware test code but skip in the simulation test code.
  4. Trigger PMA analog reset. For more information about register descriptions, refer to the E-tile Transceiver PHY User Guide.
  5. Reconfigure the registers for the Ethernet, RS-FEC, and transceiver blocks. For more information about register descriptions, refer to the E-tile Transceiver PHY User Guide.
  6. Adjust the phase offset of a recovered clock. Use PMA attribute code 0x000E in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  7. Enable SERDES. Use PMA attribute code 0x0001 in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  8. Enable internal serial loopback. Use PMA attribute code 0x0008 in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
Related Information
Level Two Title