Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

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ID 683577
Date 3/27/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 LAB and ALM Overview 2. Intel® Hyperflex™ Register 3. Intel Agilex® 7 LAB and ALM Architecture and Features 4. Document Revision History for the Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide
3. Intel Agilex® 7 LAB and ALM Architecture and Features x
3.1. LAB 3.2. ALM
3.1. LAB x
3.1.1. MLAB 3.1.2. Local and Direct Link Interconnects 3.1.3. Carry Chain Interconnects 3.1.4. LAB Control Signals
3.1.4. LAB Control Signals x
3.1.4.1. Clear Logic Control
3.2. ALM x
3.2.1. ALM Resources 3.2.2. ALM Output 3.2.3. ALM Operating Modes
3.2.3. ALM Operating Modes x
3.2.3.1. Normal Mode 3.2.3.2. Extended LUT Mode 3.2.3.3. Arithmetic Mode
3.2.3.3. Arithmetic Mode x
3.2.3.3.1. Carry Chain
1. Intel Agilex® 7 LAB and ALM Overview
2. Intel® Hyperflex™ Register
3. Intel Agilex® 7 LAB and ALM Architecture and Features
4. Document Revision History for the Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

3.2.3.1. Normal Mode

Normal mode allows two functions to be implemented in one Intel Agilex® 7 ALM, or a single function of up to six inputs.

Up to eight data inputs from the LAB local interconnect are inputs to the combinational logic.

The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs. The Intel® Quartus® Prime Compiler automatically selects the inputs to the LUT. ALMs in normal mode support register packing.

The following figure shows a combination of different input connections for the LUT mode. In your design, the Intel® Quartus® Prime software may assign different input namings during compilation.

Figure 8. ALM in Normal Mode

Combinations of functions with fewer inputs than those shown are also supported. For example, combinations of functions with the following number of inputs are supported.

  • 4 and 3
  • 3 and 3
  • 3 and 2
  • 5 and 2

For the packing of two 5-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a 4-input function with a 5-input function requires one common input (either dataa or datab).

In a sparsely used device, functions that could be placed in one ALM may be implemented in separate ALMs by the Intel® Quartus® Prime software to achieve the best possible performance. As a device begins to fill up, the Intel® Quartus® Prime software automatically uses the full potential of the Intel Agilex® 7 ALM. The Intel® Quartus® Prime Compiler automatically searches for functions using common inputs or completely independent functions to be placed in one ALM to make efficient use of device resources. In addition, you can manually control resource use by setting location assignments.

Figure 9. 6-Input LUT Mode Function in Normal Mode
Figure 10. 3-Input LUT Mode Function in Normal Mode dataa and datab are available for register packing.

You can implement any three to six input function using the following inputs:

  • datae
  • datad0
  • datac0
  • datac1
  • datad1
  • dataf
  • dataa and datab—whereby dataa and datab are shared across both LUTs to provide flexibility to implement a different function in each LUT.

Both dataa and datab inputs support the register packing feature. If you enable the register packing feature, both dataa and datab inputs or either one of the inputs bypass the LUT and directly feed into the register, depending on the packed register mode used. For Intel Agilex® 7 devices, the following types of packed register modes are supported:

  • 5-input LUT with 1 packed register path
  • 5-input LUT with 2 packed register paths
  • Two 3-input LUTs with 2 packed register paths

The 3-input LUT with 2 packed register paths is illustrated in the 3-Input LUT Mode Function in Normal Mode figure. For Intel Agilex® 7 devices, the 6-input LUT mode does not support the register packing feature.

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