Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

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ID 683577
Date 3/27/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 LAB and ALM Overview 2. Intel® Hyperflex™ Register 3. Intel Agilex® 7 LAB and ALM Architecture and Features 4. Document Revision History for the Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide
3. Intel Agilex® 7 LAB and ALM Architecture and Features x
3.1. LAB 3.2. ALM
3.1. LAB x
3.1.1. MLAB 3.1.2. Local and Direct Link Interconnects 3.1.3. Carry Chain Interconnects 3.1.4. LAB Control Signals
3.1.4. LAB Control Signals x
3.1.4.1. Clear Logic Control
3.2. ALM x
3.2.1. ALM Resources 3.2.2. ALM Output 3.2.3. ALM Operating Modes
3.2.3. ALM Operating Modes x
3.2.3.1. Normal Mode 3.2.3.2. Extended LUT Mode 3.2.3.3. Arithmetic Mode
3.2.3.3. Arithmetic Mode x
3.2.3.3.1. Carry Chain
1. Intel Agilex® 7 LAB and ALM Overview
2. Intel® Hyperflex™ Register
3. Intel Agilex® 7 LAB and ALM Architecture and Features
4. Document Revision History for the Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

3.2.3.3. Arithmetic Mode

The ALM in arithmetic mode uses two sets of two 4-input LUTs along with two dedicated full adders. The dedicated adders allow the LUTs to perform pre-adder logic. Therefore, each adder can add the output of two 4-input functions.

Arithmetic mode also offers clock enable, counter enable, synchronous up and down control, add and subtract control, and synchronous clear.

The clear and clock enable options are LAB-wide signals that affect all registers in the LAB. You can individually disable or enable these signals for each pair of registers in an adaptive LUT (ALUT). The Intel® Quartus® Prime software automatically places any registers that are not used by the counter into other LABs.

Figure 12.  Intel Agilex® 7 ALM in Arithmetic Mode

Section Content
Carry Chain

Level Two Title