Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

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ID 683577
Date 3/27/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 LAB and ALM Overview 2. Intel® Hyperflex™ Register 3. Intel Agilex® 7 LAB and ALM Architecture and Features 4. Document Revision History for the Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide
3. Intel Agilex® 7 LAB and ALM Architecture and Features x
3.1. LAB 3.2. ALM
3.1. LAB x
3.1.1. MLAB 3.1.2. Local and Direct Link Interconnects 3.1.3. Carry Chain Interconnects 3.1.4. LAB Control Signals
3.1.4. LAB Control Signals x
3.1.4.1. Clear Logic Control
3.2. ALM x
3.2.1. ALM Resources 3.2.2. ALM Output 3.2.3. ALM Operating Modes
3.2.3. ALM Operating Modes x
3.2.3.1. Normal Mode 3.2.3.2. Extended LUT Mode 3.2.3.3. Arithmetic Mode
3.2.3.3. Arithmetic Mode x
3.2.3.3.1. Carry Chain
1. Intel Agilex® 7 LAB and ALM Overview
2. Intel® Hyperflex™ Register
3. Intel Agilex® 7 LAB and ALM Architecture and Features
4. Document Revision History for the Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

3.2.2. ALM Output

The general routing outputs in each ALM drive the local, row, and column routing resources. Six ALM outputs, including two fast output paths, can drive column, row, or direct link routing connections.

The LUT, adder, or register output can drive the ALM outputs. Both the LUT or adder and the ALM register can drive out of the ALM simultaneously.

Register packing improves device utilization by allowing unrelated register and combinational logic to be packed into a single ALM. The ALM can also drive out registered and unregistered versions of the LUT or adder output.

The following figure shows the Intel Agilex® 7 ALM connectivity. In the Intel® Quartus® Prime Resource Property Editor, the entire ALM connection is simplified. Some routings will be routed internally by the Intel® Quartus® Prime software.

Figure 7.  Intel Agilex® 7 ALM Connection Details
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