Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

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ID 683577
Date 3/27/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 LAB and ALM Overview 2. Intel® Hyperflex™ Register 3. Intel Agilex® 7 LAB and ALM Architecture and Features 4. Document Revision History for the Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide
3. Intel Agilex® 7 LAB and ALM Architecture and Features x
3.1. LAB 3.2. ALM
3.1. LAB x
3.1.1. MLAB 3.1.2. Local and Direct Link Interconnects 3.1.3. Carry Chain Interconnects 3.1.4. LAB Control Signals
3.1.4. LAB Control Signals x
3.1.4.1. Clear Logic Control
3.2. ALM x
3.2.1. ALM Resources 3.2.2. ALM Output 3.2.3. ALM Operating Modes
3.2.3. ALM Operating Modes x
3.2.3.1. Normal Mode 3.2.3.2. Extended LUT Mode 3.2.3.3. Arithmetic Mode
3.2.3.3. Arithmetic Mode x
3.2.3.3.1. Carry Chain
1. Intel Agilex® 7 LAB and ALM Overview
2. Intel® Hyperflex™ Register
3. Intel Agilex® 7 LAB and ALM Architecture and Features
4. Document Revision History for the Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

4. Document Revision History for the Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

Document Version Changes
2023.03.27 Updated product family name to "Intel Agilex® 7".
2022.05.24 Updated Figure: Intel Agilex® 7 ALM High-Level Block Diagram.
2019.11.14 Updated the description in the LAB Control Signals section.
2019.10.01
  • Updated the details for the synchronous and asynchronous clear signals in the Clear Logic Control section.
  • Updated Figure: Intel Agilex® 7 LAB Structure and Interconnects Overview.
  • Updated Figure: Intel Agilex® 7 LAB Local and Direct Link Interconnects.
  • Updated Figure: Intel Agilex® 7 ALM Connection Details.
  • Updated Figure: Intel Agilex® 7 LAB-Wide Control Signals.
  • Updated Figure: Intel Agilex® 7 ALM High-Level Block Diagram.
  • Removed the Time Borrowing and Latch Modes section.
2019.04.02 Initial release.
Level Two Title