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Ixiasoft
3.2.1. ALM Resources
Each ALM contains a variety of LUT-based resources that can be divided between two combinational adaptive LUTs (ALUTs), a two-bits full adder, and four registers.
With up to eight inputs for the two combinational ALUTs, one ALM can implement various combinations of two functions. This adaptability allows an ALM to be completely backward-compatible with four input LUT architectures. One ALM can also implement a subset of eight input functions.
One ALM contains four programmable registers. Each register has the following ports:
- Data in
- Data out
- Normal LAB clock
- Delayed LAB clock
- Clock enable
- Synchronous clear
- Asynchronous clear
Global signals, general-purpose I/O (GPIO) pins, or any internal logic can drive the clock enable signal, clock, and asynchronous or synchronous clear control signals of an ALM register. The clock enable signal has priority over synchronous reset signal.
For combinational functions, the registers are bypassed and the output of the look-up table (LUT) and adders drives directly to the outputs of an ALM. Two fast outputs are available for 6 LUT outputs and bottom 5 LUT outputs to bypass the output mux and connect to another LAB for critical path adjustment.
Figure 6. Intel Agilex® 7 ALM High-Level Block Diagram