Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

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ID 683577
Date 3/27/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 LAB and ALM Overview 2. Intel® Hyperflex™ Register 3. Intel Agilex® 7 LAB and ALM Architecture and Features 4. Document Revision History for the Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide
3. Intel Agilex® 7 LAB and ALM Architecture and Features x
3.1. LAB 3.2. ALM
3.1. LAB x
3.1.1. MLAB 3.1.2. Local and Direct Link Interconnects 3.1.3. Carry Chain Interconnects 3.1.4. LAB Control Signals
3.1.4. LAB Control Signals x
3.1.4.1. Clear Logic Control
3.2. ALM x
3.2.1. ALM Resources 3.2.2. ALM Output 3.2.3. ALM Operating Modes
3.2.3. ALM Operating Modes x
3.2.3.1. Normal Mode 3.2.3.2. Extended LUT Mode 3.2.3.3. Arithmetic Mode
3.2.3.3. Arithmetic Mode x
3.2.3.3.1. Carry Chain
1. Intel Agilex® 7 LAB and ALM Overview
2. Intel® Hyperflex™ Register
3. Intel Agilex® 7 LAB and ALM Architecture and Features
4. Document Revision History for the Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

1. Intel Agilex® 7 LAB and ALM Overview

The logic array block (LAB) is composed of basic building blocks known as adaptive logic modules (ALMs). You can configure the LABs to implement logic functions, arithmetic functions, and register functions.

You can use half of the available LABs in the Intel Agilex® 7 devices as memory LABs (MLABs). Certain devices may have a higher MLAB ratio.

The Intel® Quartus® Prime software and other supported third-party synthesis tools automatically choose the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions.

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