AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683565
Date 6/23/2021
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer Test 1.3.2. Transmitter Transport Layer Test 1.3.3. Deterministic Latency - Subclass 1
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1.3.2. Transmitter Transport Layer Test

To check the data integrity of the payload data stream through the transmitter (TX) JESD204C Intel® FPGA IP and transport layer, the DAC is configured to PRBS23 test pattern. The DAC is also set to operate with the same configuration as set in the JESD204C Intel® FPGA IP of the FPGA. The PRBS generator in the JESD204C Intel® FPGA IP example design generates the PRBS23 patterns. The PRBS checker in the DAC transport layer checks the PRBS23 data integrity.

The figure below shows the conceptual test setup for data integrity checking.

Figure 4. Data Integrity Check Using PRBS Checker
Table 2.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria
TL.1 Check the transport layer mapping of the data channel using PRBS test pattern. The following signals in <ip_variant_name>_base.v are tapped:
  • j204c_tx_avst_ready
  • j204c_tx_avst_valid
  • j204c_tx_avst_data [(M*S*WIDTH_MULP*N)-1:0] 1 2 3 4

The txframe_clk is used as the sampling clock for the Signal Tap.

  • The j204c_tx_avst_valid and j204c_tx_avst_ready signals are asserted.
TL.2 Check the data sample PRBS test using PRBS23 data.
FPGA-generated PRBS23 patterns are checked using the AD9081 API functions and the following steps are used to complete the tests:
  • Check for HMC7044 PLL lock.
  • Check for AD9081 JRx link up.
  • Call sample PRBS test using API function.
  • Call sample PRBS result using API function.
  • Check for number of channels passing.

    For example, if M = 8, then 2 virtual converters are mapped to each channels.

    M0M1 to channel 0, M1M2 to channel 1, etc.

The following registers in AD9081 are monitored for PRBS23 test pattern:
  • JESD204C RECEIVER_PRBS_LANE_UPDATE_ERROR_COUNT
  • JESD204C RECEIVER_PRBS_LANE_ERROR_FLAG
  • JESD204C_RECEIVER_PRBS_LANE_INVALID_DATA_FLAG

The read datapath PRBS registers from 0x2063 to 0x2069 using the API functions.

  • Error flag of I and Q channels should be ‘0’.
  • Invalid data flag of I and Q channels should be ‘0’.
  • Error counts of I and Q channels should be ‘0’.
Note: The results for sample PRBS test are logged into a .csv file generated in the Linux machine.
Figure 5. PRBS Data Pattern Diagram
1 M is the number of converters.
2 S is the number of transmitted samples per converter per frame.
3 WIDTH_MULP is the data width multiplier between the application layer and transport layer.
4 N is the number of conversion bits per converter.
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