AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683565
Date 6/23/2021
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer Test 1.3.2. Transmitter Transport Layer Test 1.3.3. Deterministic Latency - Subclass 1
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1.4. JESD204C Intel® FPGA IP and DAC Configurations

The JESD204C Intel® FPGA IP parameters (L, M, and F) in this hardware checkout are natively supported by the AD9081 device. The transceiver data rate, sampling clock, and other JESD204C parameters comply with the AD9081 operating conditions.

The hardware checkout testing implements the JESD204C Intel® FPGA IP with the following parameter configuration.

Global setting for all configuration:
  • CF = 0
  • CS = 0
  • Subclass = 1
  • SH_CONFIG = CRC-12
  • FPGA Management Clock (MHz) = 100
Note: The other configurations are retained at default values.
Table 4.  Parameter Configuration
No. JESD204C DAC Mode L M F S HD E N NP DAC Sampling Clock

(MHz)

 FPGA Device Clock

(MHz)

 Course Interpolation Fine Interpolation Lane Rate

(Gbps)

 Data Pattern
1 1 1 4 8 1 0 1 16 16 11796.48 245.76 12 4 16.22016 PRBS23
2 2 1 2 4 1 0 1 16 16 11796.48 245.76 12 4 16.22016 PRBS23
3 3 2 8 8 1 0 1 16 16 11796.48 245.76 12 2 16.22016 PRBS23
4 5 2 4 4 1 0 1 16 16 11796.48 245.76 12 2 16.22016 PRBS23
5 6 2 2 2 1 0 1 16 16 11796.48 245.76 12 1 16.22016 PRBS23
6 7 3 12 8 1 0 1 16 16 5898.24 245.76 12 2 16.22016 PRBS23
7 8 3 6 4 1 0 1 16 16 11796.48 245.76 12 2 16.22016 PRBS23
8 9 4 8 4 1 0 1 16 16 11796.48 245.76 12 2 16.22016 PRBS23
9 10 4 4 2 1 0 1 16 16 11796.48 245.76 12 1 16.22016 PRBS23
10 11 4 16 8 1 0 1 16 16 8847.36 184.32 12 4 12.16512 PRBS23
11 12 4 2 1 1 0 1 16 16 2949.12 184.32 2 1 12.16512 PRBS23
12 14 6 12 4 1 0 1 16 16 8847.36 184.32 12 2 12.16512 PRBS23
13 15 8 8 2 1 0 1 16 16 8847.36 184.32 12 1 12.16512 PRBS23
14 16 8 16 4 1 0 1 16 16 5898.24 184.32 8 2 12.16512 PRBS23
15 17 8 4 1 1 0 1 16 16 11796.48 184.32 8 1 12.16512 PRBS23
16 18 8 2 1 2 0 1 16 16 11796.48 184.32 4 1 12.16512 PRBS23
17 20 8 1 1 4 0 1 16 16 5898.24 184.32 1 1 12.16512 PRBS23
18 21 4 8 8 2 0 1 16 16 5898.24 245.76 12 2 8.11008 PRBS23
19 30 4 4 4 2 0 1 16 16 5898.24 184.32 8 1 12.16512 PRBS23
20 31 4 4 8 4 0 1 16 16 5898.24 184.32 8 1 12.16512 PRBS23
21 33 4 2 8 8 0 1 16 16 5898.24 184.32 8 1 12.16512 PRBS23
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