AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683565
Date 6/23/2021
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer Test 1.3.2. Transmitter Transport Layer Test 1.3.3. Deterministic Latency - Subclass 1
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1.1. Hardware and Software Requirements

The hardware checkout test requires the following hardware and software tools:

  • Intel® Stratix® 10 TX Signal Integrity (SI) Development Kit (Production Rev B Edition) (1ST280EY2F55E1VG) with 12 V power adaptor
  • Analog Devices AD9081 MxFE* EVM (Rev C, R1 silicon)
  • Voltage translator circuit
  • SMA (Male) to SMP (Female) cables
  • SMA (Male) to SMA (Male) cables
  • 3.3V DC power supply for the voltage translator circuit
  • Intel® Quartus® Prime Pro Edition software version 20.3
  • AD9081_API version 1.0.6 (Linux application, required for AD9081 EVM configuration)
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