AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683565
Date 6/23/2021
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer Test 1.3.2. Transmitter Transport Layer Test 1.3.3. Deterministic Latency - Subclass 1
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1.3.1. Transmitter Data Link Layer Test

This test area covers the test cases for tx_rst_n and link establishment.

On link start up, after tx_rst_n is deasserted, the JESD204C Intel® FPGA IP starts the link operation. In typical user application, all run-time register should be configured when the Avalon® memory-mapped configuration space is out of reset and before the txlink_clk and txframe_clk are out of reset. For link establishment, AD9081 configuration is done and jrx_dl_state is monitored to check passing criteria of the link.

Table 1.  Data Link Layer Test Cases

Test Case

Objective

Description

Passing Criteria

LL.1

Check if j204c_tx_rst_n is deasserted after the completion of reset sequence.

The following signals in <ip_variant_name>_base.v are tapped:

  • j204c_tx_rst_n
  • j204c_tx_int

The txlink_clk is used as the sampling clock for the Signal Tap.

  • The transmitter error status is read from tx_err register.
  • The j204c_tx_rst_n signal is deasserted after power on.
  • The j204c_tx_int signal stays low if there is no error.
  • The tx_err register (addr - 0x60) of JESD204C Intel® FPGA IP should be read as 0x0000000.
LL.2

To verify link establishment from AD9081 after reset is released. This confirms sync header (SH) alignment, extended multiblock alignment completion.

The following signals from AD9081 is monitored for link establishment:
  • jrx_dl_204c_state
  • jrx_204c_CRC_IRQ
  • The jrx_dl_204c_state (0x055e register of AD9081) signal should reach state 110 for link establishment after SH alignment and extended multiblock alignment.
  • The jrx_204c_CRC_IRQ signal should not assert due to cyclic redundancy check (CRC) errors.
Note: j204c_tx_int is mapped to tx_link_error[0]. This tx_link_error[0] is captured in Signal Tap to verify the interrupt signal.
Figure 3. TDL.1 Signal Tap Capture
Level Two Title