AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683565
Date 6/23/2021
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer Test 1.3.2. Transmitter Transport Layer Test 1.3.3. Deterministic Latency - Subclass 1
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1.2. Hardware Setup

An Intel® Stratix® 10 TX SI Development Kit (Production Rev B Edition) is used with the ADI AD9081 daughter card module installed to the FMC+ connector of the development board.

  • The AD9081 EVM derives power from the Intel® Stratix® 10 board through the FMC+ connector.
  • The E-tile transceiver reference clock of the FPGA is also supplied by the Silicon Labs Si5341 programmable clock generator present in the Intel® Stratix® 10 TX SI development kit.
  • The Si5341 programmable clock generator provides a reference clock to the HMC7044 programmable clock generator present in the AD9081 EVM through FPGA (to convert differential clock from Si5431 to single ended clock for HMC7044) and SMA to SMP cable.
  • The HMC7044 programmable clock generator provides the AD9081 device reference clock. The phase-locked loop (PLL) present in the AD9081 device generates the desired DAC sampling clock from the device reference clock.
  • The PLL reference clock of the JESD204C Intel® FPGA IP is supplied by the HMC7044 programmable clock generator through the FMC+ connector.
  • For Subclass 1, the HMC7044 clock generator generates the SYSREF signal for the AD9081 device and for the JESD204C Intel® FPGA IP through the FMC+ connector.
  • The tx_dl_signal signal is connected in between the output of the FPGA and the DAC 0 input of AD9081 through a voltage level translator circuit (refer to Figure 7) with the SMA to SMA cables to measure the deterministic latency.
Note: Intel® recommends the SYSREF to be provided by the clock generator that sources the JESD204C Intel® FPGA IP device clock and sampling clock to DAC.
Figure 1. Hardware Setup

The system-level diagram below shows how the different modules are connected in this design.

Figure 2. System Diagram

In this setup, where L = 8, M = 16, and F = 4, the data rate of transceiver lanes is 12.16512 Gbps. The clock and SYSREF source structure for the FPGA and DAC is explained below and illustrated in Figure 2.

The Si5341 out8 generates 184.32 MHz clock to E-tile transceiver reference clock. The 122.88 MHz differential output clock generated by the Si5341 out2 is fed to the FPGA and taken out of the FPGA as a single ended clock. This single ended clock is routed to CLK OUT SMA port J33 in the development kit and connected to HMC7044 (EXT_HMCREF SMP port) in the AD9081 EVM through the SMA to SMP cable. The HMC7044 takes the 122.88 MHz reference clock and generates 122.88 MHz for the device clock CLKIN of AD9081 and a periodic SYSREF signal of 5.76 MHz for the SYSREF input of AD9081. The HMC7044 also generates 184.32 MHz for the core PLL reference clock of the FPGA's JESD204C Intel® FPGA IP and a periodic SYSREF signal of 5.76 MHz for the JESD204C Intel® FPGA IP through the FMC+ connector.

The JESD204C Intel® FPGA IP is instantiated in Duplex mode but only the transmitter path is used. For FCLK_MULP = 1, WIDTH_MULP = 4, S = 1, the core PLL generates 92.16 MHz link clock and 184.32 MHz frame clock.

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