Visible to Intel only — GUID: orl1515470823746
Ixiasoft
Visible to Intel only — GUID: orl1515470823746
Ixiasoft
4.3.1. Device Constraints
The following table summarizes the most common AMD* Xilinx* device constraints and Intel® FPGA equivalent device constraints.
AMD* Xilinx* Constraint | Intel® FPGA Constraint | Description | |
---|---|---|---|
Assignment Name | QSF Variable | ||
DRIVE | Current Strength | CURRENT_STRENGTH_NEW | Controls the output pin current value |
SLEW | Slew Rate | SLEW_RATE | Turns on Fast Slew Rate Control. |
IOB | Fast Input Register Fast Output Register |
FAST_INPUT_REGISTER FAST_OUTPUT_REGISTER |
Specifies whether the Compiler places a register in the device's IOB. |
IOSTANDARD | IO Standard | IO_STANDARD | Specifies the I/O standard for an I/O pin |
KEEP | Implement as Output of Logic Cell | "attribute keep" (VHDL) "synthesis keep" (Verilog) |
Prevents a net from either being absorbed by a block or synthesized out. |
To set or modify a device constraint, use the Quartus® Prime Assignment Editor. Alternatively, you can edit the .qsf file.