Visible to Intel only — GUID: eis1395305814278
Ixiasoft
Visible to Intel only — GUID: eis1395305814278
Ixiasoft
4.2.1.2.6. Byte Enable
The following table compares byte enable implementation in AMD* Xilinx* and Intel® FPGA RAMs
Differences | AMD* Xilinx* RAM | Intel® FPGA RAM | |||||||||
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Controlling signals | The WEA[n:0] signal controls the byte enable. Each bit in WEA[n:0] acts as a write enable for the corresponding input data byte. |
Uses two signals, write enable (wren) and byte enable (byteena).
To control which byte to write, assert the wren signal and the specific bit of the byteena signal. For example, in a RAM block in x16 mode:
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Input data width support | Support multiples of 8 or 9 bits. | Support multiples of 5, 8, 9, 10 bits. For configurations smaller than two bytes wide, the write_enable or clock_enable signals control the write operation.17 | |||||||||
Output value of masked byte when performing read-during-write to the same location. | Output depends on read-during-write configuration:
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Output depends on the type of memory block:
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