AN 829: PCI Express* Avalon® -MM DMA Reference Design

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ID 683554
Date 6/11/2018
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Document Table of Contents
Document Table of Contents x
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design x
1.1. Introduction 1.2. Working with the Reference Design 1.3. Understanding PCI Express Throughput 1.4. Document Revision History for AN 829: PCI Express* Avalon® -MM DMA Reference Design
1.1. Introduction x
1.1.1. DMA Reference Design Hardware and Software Requirements 1.1.2. Avalon® -MM DMA Bridge Module Descriptions
1.2. Working with the Reference Design x
1.2.1. Project Hierarchy 1.2.2. Parameter Settings for PCI Express Hard IP Variations 1.2.3. PCIe* Avalon® -MM DMA Reference Design Platform Designer Systems 1.2.4. DMA Procedure Steps 1.2.5. Setting Up the Hardware 1.2.6. Programming the Intel® Cyclone® 10 GX FPGA Oscillator 1.2.7. Installing the DMA Test Driver and Running the Linux DMA Software
1.3. Understanding PCI Express Throughput x
1.3.1. Throughput for Posted Writes 1.3.2. Throughput for Reads 1.3.3. Throughput Differences for On-Chip and External Memory
1.3.1. Throughput for Posted Writes x
1.3.1.1. Specifying the Maximum Payload Size
1.3.2. Throughput for Reads x
1.3.2.1. Understanding Throughput Measurement
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design

1.2.6. Programming the Intel® Cyclone® 10 GX FPGA Oscillator

The Intel® Cyclone® 10 GX Development Kit includes a programmable oscillator that you must set up before you can run the reference design for Intel® Cyclone® 10 GX devices. A ClockController GUI allows you to import the correct settings.
  1. Locate the Kit Collateral (zip) link in the Documentation area of the Intel® Cyclone® 10 GX FPGA Development Kit web page.
  2. Use this link to download cyclone-10-gx-kit-collateral.zip
  3. Unzip cyclone-10-gx-kit-collateral.zip to a working directory on computer number 2.
  4. To bring up the Clock Controller dialog box, type the following commands: 
    % cd <install_dir>/cyclone-10-gx-collateral/examples/board_test_system/
% ./ClockController.sh
    Figure 6. Clock Controller GUI in Initial State
  5. In the Clock Controller GUI, click Import.
  6. Browse to the <install_dir>/cyclone-10-gx-collateral/examples/board_test_system/ directory and select U64-Registers.txt.
  7. To import the register settings, click Open.
    The message, Si5332 Register Map is imported successfully displays. You should see the clock settings shown below.
    Figure 7. Clock Settings for Intel® Cyclone® 10 GX FPGA Development Kit
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