AN 829: PCI Express* Avalon® -MM DMA Reference Design

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ID 683554
Date 6/11/2018
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Document Table of Contents
Document Table of Contents x
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design x
1.1. Introduction 1.2. Working with the Reference Design 1.3. Understanding PCI Express Throughput 1.4. Document Revision History for AN 829: PCI Express* Avalon® -MM DMA Reference Design
1.1. Introduction x
1.1.1. DMA Reference Design Hardware and Software Requirements 1.1.2. Avalon® -MM DMA Bridge Module Descriptions
1.2. Working with the Reference Design x
1.2.1. Project Hierarchy 1.2.2. Parameter Settings for PCI Express Hard IP Variations 1.2.3. PCIe* Avalon® -MM DMA Reference Design Platform Designer Systems 1.2.4. DMA Procedure Steps 1.2.5. Setting Up the Hardware 1.2.6. Programming the Intel® Cyclone® 10 GX FPGA Oscillator 1.2.7. Installing the DMA Test Driver and Running the Linux DMA Software
1.3. Understanding PCI Express Throughput x
1.3.1. Throughput for Posted Writes 1.3.2. Throughput for Reads 1.3.3. Throughput Differences for On-Chip and External Memory
1.3.1. Throughput for Posted Writes x
1.3.1.1. Specifying the Maximum Payload Size
1.3.2. Throughput for Reads x
1.3.2.1. Understanding Throughput Measurement
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design

1.2.3. PCIe* Avalon® -MM DMA Reference Design Platform Designer Systems

The following images show the Platform Designer systems for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
Figure 3.  Intel® Arria® 10 GX DMA Reference Design Platform Designer System
Figure 4.  Intel® Cyclone® 10 GX GX DMA Reference Design Platform Designer System
Figure 5.  Intel® Stratix® 10 GX DMA Reference Design Platform Designer SystemThe Intel® Stratix® 10 design includes pipeline components and clock-crossing logic that are not present in the other devices.
Table 10.   Platform Designer Port Descriptions
Port Function Description

rxm_bar2

or

rxm_bar4

Avalon® -MM port

This is an Avalon® -MM master port. The PCIe* host accesses the memory through PCIe* BAR2 for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. The host accesses the memory through PCIe* BAR4 for Intel® Stratix® 10 devices. These BARs connect to both on-chip and external memory.

In a typical application, system software controls this BAR to initialize random data in the external memory. Software also reads the data back to verify correct operation.

txs TX Avalon® -MM Slave

This is an Avalon® -MM slave port. In a typical application, an Avalon® -MM master controls this port to send memory reads and writes to the PCIe* domain.

When the DMA completes operation, the Descriptor Controller uses this port to write DMA status back to the descriptor table in the PCIe* domain. The Descriptor Controller also uses this port to send MSI interrupts upstream.

dma_rd_master Read Data Mover

This is an Avalon® -MM master port. The Read Data Mover uses this Avalon® -MM master to move data from the PCIe* domain to either the on-chip or external memory. The Read Data Mover also uses this port to fetch descriptors from the PCIe* domain and write them to the FIFO in the Descriptor Controller.

The design includes separate descriptor tables for read and write descriptors. Consequently, the dma_rd_master port connects to wr_dts_slave for the write DMA descriptor FIFO and rd_dts_slave for the read DMA descriptor FIFO.

dma_wr_master Write Data Mover

This is an Avalon® -MM master port. The Write Data Mover uses this Avalon® -MM master to read data from either the on-chip or external memory and then write data to the PCIe* domain.

The external memory controller is a single-port RAM. Consequently, the Write Data Mover and the Read Data Mover must share this port to assess external memory.

wr_dts_slave

rd_dts_slave

FIFO in Descriptor Controller

These are Avalon® -MM slave ports for the FIFOs in the Descriptor Controller. When the Read Data Mover fetches the descriptors from system memory, the Read Data Mover writes the descriptors to the FIFO using the wr_dts_slave and rd_dts_slave ports.

wr_dcm_master

rd_dcm_master

Control module in Descriptor Controller

The Descriptor Controller control module includes one transmit and one receive port for the read and write DMAs. The receive port connects to RXM_BAR0. The transmit port connects to the txs.

The receive path from the RXM_BAR0 connects internally. RXM_BAR0 is not shown in the Platform Designer connections panel. For the transmit path, both read and write DMA ports connect to the txs externally. These ports are visible in the Platform Designer connections panel.

Internal connection, not shown Avalon® -MM port This Avalon® -MM master port passes the memory access from the PCIe* host to PCIe* BAR0. The host uses this port to program the Descriptor Controller. Because this reference design includes the Descriptor Controller as an internal module, Platform Designer does not display this port on the top-level connections panel.
onchip_memory2_0 64 KB Dual Port RAM

This is a 64-KB dual-port on-chip memory. The address range is 0x0800_0000-0x0800_FFFF on the Avalon® -MM bus. This address is the source address for write DMAs or destination address for read DMAs.

To prevent data corruption, software divides the memory into separate regions for reads and writes. The regions do not overlap.

Intel DDR3 or DDR4 controller

DDR3 or DDR4 Controller

 This is a single-port DDR3 or DDR4 controller.
Level Two Title