AN 829: PCI Express* Avalon® -MM DMA Reference Design

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ID 683554
Date 6/11/2018
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Document Table of Contents
Document Table of Contents x
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design x
1.1. Introduction 1.2. Working with the Reference Design 1.3. Understanding PCI Express Throughput 1.4. Document Revision History for AN 829: PCI Express* Avalon® -MM DMA Reference Design
1.1. Introduction x
1.1.1. DMA Reference Design Hardware and Software Requirements 1.1.2. Avalon® -MM DMA Bridge Module Descriptions Read Data Mover Write Data Mover DMA Descriptor Controller TX Slave RX Master (Internal Port for BAR0 Control)
1.2. Working with the Reference Design x
1.2.1. Project Hierarchy 1.2.2. Parameter Settings for PCI Express Hard IP Variations 1.2.3. PCIe* Avalon® -MM DMA Reference Design Platform Designer Systems 1.2.4. DMA Procedure Steps 1.2.5. Setting Up the Hardware 1.2.6. Programming the Intel® Cyclone® 10 GX FPGA Oscillator 1.2.7. Installing the DMA Test Driver and Running the Linux DMA Software
1.3. Understanding PCI Express Throughput x
1.3.1. Throughput for Posted Writes 1.3.2. Throughput for Reads 1.3.3. Throughput Differences for On-Chip and External Memory
1.3.1. Throughput for Posted Writes x
1.3.1.1. Specifying the Maximum Payload Size
1.3.2. Throughput for Reads x
1.3.2.1. Understanding Throughput Measurement
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design

1.1.2. Avalon® -MM DMA Bridge Module Descriptions

The Avalon-MM interface with DMA includes the following modules:

Figure 2.  PCIe* Avalon® -MM DMA Reference Design Block DiagramThis bock diagram shows both the on-chip memory and external memory options.

Read Data Mover

The Read Data Mover sends memory read Transaction Layer Packet (TLPs) upstream. After the Read Data Mover receives the Completion, the Read Data Mover writes the received data to the on-chip or external memory.

Write Data Mover

The Write Data Mover reads data from the on-chip or external memory and sends the data upstream using memory write TLPs on the PCIe* link.

DMA Descriptor Controller

The Descriptor Controller module manages the DMA read and write operations.

Host software programs internal registers in the Descriptor Controller with the location and size of the descriptor table residing in the host system memory through the Avalon® -MM RX master port. Based on this information, the Descriptor Controller directs the Read Data Mover to copy the entire table to local FIFOs for execution. The Descriptor Controller sends completion status upstream via the Avalon® TX slave (TXS) port.

You can also use your own external descriptor controller to manage the Read and Write Data Movers. However, you cannot change the interface between your own external controller and the Read and Write Data Movers embedded in the reference design.

TX Slave

The TX Slave module propagates Avalon® -MM reads and writes upstream. External Avalon® -MM masters, including the DMA control master, can access system memory using the TX Slave. The DMA Controller uses this path to update the DMA status upstream, using Message Signaled Interrupt (MSI) TLPs.

RX Master (Internal Port for BAR0 Control)

The RX Master module propagates single dword read and write TLPs from the Root Port to the Avalon® -MM domain via a 32-bit Avalon® -MM master port. Software instructs the RX Master to send control, status, and descriptor information to Avalon® -MM slaves, including the DMA control slave. The RX Master port is an internal port that not visible in Platform Designer.

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