Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

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ID 683552
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. System Debugging Tools Overview 2. Analyzing and Debugging Designs with System Console 3. Debugging Transceiver Links 4. Quick Design Debugging Using Signal Probe 5. Design Debugging with the Signal Tap Logic Analyzer 6. In-System Debugging Using External Logic Analyzers 7. In-System Modification of Memory and Constants 8. Design Debugging Using In-System Sources and Probes A. Intel® Quartus® Prime Standard Edition User Guides
1. System Debugging Tools Overview x
1.1. System Debugging Tools Portfolio 1.2. Tools for Monitoring RTL Nodes 1.3. Stimulus-Capable Tools 1.4. Virtual JTAG Interface Intel® FPGA IP 1.5. System-Level Debug Fabric 1.6. System Debugging Tools Overview Revision History
1.1. System Debugging Tools Portfolio x
1.1.1. System Debugging Tools Comparison 1.1.2. Suggested Tools for Common Debugging Requirements 1.1.3. Debugging Ecosystem
1.2. Tools for Monitoring RTL Nodes x
1.2.1. Resource Usage 1.2.2. Pin Usage 1.2.3. Usability Enhancements
1.2.1. Resource Usage x
1.2.1.1. Overhead Logic 1.2.1.2. Resource Estimation
1.2.2. Pin Usage x
1.2.2.1. For Signal Tap Logic Analyzer 1.2.2.2. For Signal Probe 1.2.2.3. For Logic Analyzer Interface
1.2.3. Usability Enhancements x
1.2.3.1. Incremental Compilation 1.2.3.2. Incremental Routing 1.2.3.3. Automation Via Scripting 1.2.3.4. Remote Debugging
1.3. Stimulus-Capable Tools x
1.3.1. In-System Sources and Probes 1.3.2. In-System Memory Content Editor 1.3.3. System Console
1.3.1. In-System Sources and Probes x
1.3.1.1. Push Button Functionality
1.3.2. In-System Memory Content Editor x
1.3.2.1. Generate Test Vectors
1.3.3. System Console x
1.3.3.1. Test Signal Integrity 1.3.3.2. Board Bring-Up and Verification 1.3.3.3. Test Link Signal Integrity with Transceiver Toolkit
2. Analyzing and Debugging Designs with System Console x
2.1. Introduction to System Console 2.2. System Console Debugging Flow 2.3. IP Cores that Interact with System Console 2.4. Starting System Console 2.5. System Console GUI 2.6. System Console Commands 2.7. Running System Console in Command-Line Mode 2.8. System Console Services 2.9. Working with Toolkits 2.10. ADC Toolkit 2.11. System Console Examples and Tutorials 2.12. On-Board Intel® FPGA Download Cable II Support 2.13. MATLAB* and Simulink* in a System Verification Flow 2.14. Deprecated Commands 2.15. Analyzing and Debugging Designs with the System Console Revision History
2.3. IP Cores that Interact with System Console x
2.3.1. Services Provided through Debug Agents
2.4. Starting System Console x
2.4.1. Starting System Console from Nios® II Command Shell 2.4.2. Starting Stand-Alone System Console 2.4.3. Starting System Console from Platform Designer (Standard) 2.4.4. Starting System Console from Intel® Quartus® Prime 2.4.5. Customizing Startup
2.5. System Console GUI x
2.5.1. System Explorer Pane
2.8. System Console Services x
2.8.1. Locating Available Services 2.8.2. Opening and Closing Services 2.8.3. SLD Service 2.8.4. In-System Sources and Probes Service 2.8.5. Monitor Service 2.8.6. Device Service 2.8.7. Design Service 2.8.8. Bytestream Service 2.8.9. JTAG Debug Service
2.8.3. SLD Service x
2.8.3.1. SLD Commands
2.8.4. In-System Sources and Probes Service x
2.8.4.1. In-System Sources and Probes Commands
2.8.5. Monitor Service x
2.8.5.1. Monitor Commands
2.8.6. Device Service x
2.8.6.1. Device Commands
2.8.7. Design Service x
2.8.7.1. Design Service Commands
2.8.8. Bytestream Service x
2.8.8.1. Bytestream Commands
2.8.9. JTAG Debug Service x
2.8.9.1. JTAG Debug Commands
2.9. Working with Toolkits x
2.9.1. Convert your Dashboard Scripts to Toolkit API 2.9.2. Creating a Toolkit Description File 2.9.3. Registering a Toolkit 2.9.4. Launching a Toolkit 2.9.5. Matching Toolkits with IP Cores 2.9.6. Toolkit API
2.9.6. Toolkit API x
2.9.6.1. Customizing Toolkit API Widgets 2.9.6.2. Toolkit API Script Examples 2.9.6.3. Toolkit API GUI Example 2.9.6.4. Toolkit API Commands 2.9.6.5. Toolkit API Properties
2.9.6.3. Toolkit API GUI Example x
2.9.6.3.1. Toolkit API GUI Example .tcl File
2.9.6.4. Toolkit API Commands x
2.9.6.4.1. toolkit_register 2.9.6.4.2. toolkit_open 2.9.6.4.3. get_quartus_ini 2.9.6.4.4. toolkit_get_context 2.9.6.4.5. toolkit_get_types 2.9.6.4.6. toolkit_get_properties 2.9.6.4.7. toolkit_add 2.9.6.4.8. toolkit_get_property 2.9.6.4.9. toolkit_set_property 2.9.6.4.10. toolkit_remove 2.9.6.4.11. toolkit_get_widget_dimensions
2.9.6.5. Toolkit API Properties x
2.9.6.5.1. Widget Types and Properties 2.9.6.5.2. barChart Properties 2.9.6.5.3. button Properties 2.9.6.5.4. checkBox Properties 2.9.6.5.5. comboBox Properties 2.9.6.5.6. dial Properties 2.9.6.5.7. fileChooserButton Properties 2.9.6.5.8. group Properties 2.9.6.5.9. label Properties 2.9.6.5.10. led Properties 2.9.6.5.11. lineChart Properties 2.9.6.5.12. list Properties 2.9.6.5.13. pieChart Properties 2.9.6.5.14. table Properties 2.9.6.5.15. text Properties 2.9.6.5.16. textField Properties 2.9.6.5.17. timeChart Properties 2.9.6.5.18. xyChart Properties
2.10. ADC Toolkit x
2.10.1. ADC Toolkit Terms 2.10.2. Setting the Frequency of the Reference Signal 2.10.3. Tuning the Signal Generator 2.10.4. Running a Signal Quality Test 2.10.5. Running a Linearity Test 2.10.6. ADC Toolkit Data Views
2.11. System Console Examples and Tutorials x
2.11.1. Nios® II Processor Example
2.11.1. Nios® II Processor Example x
2.11.1.1. Processor Commands
2.13. MATLAB* and Simulink* in a System Verification Flow x
2.13.1. Supported MATLAB* API Commands 2.13.2. High Level Flow
3. Debugging Transceiver Links x
3.1. Channel Manager 3.2. Transceiver Debugging Flow Walkthrough 3.3. Modifying the Design to Enable Transceiver Debug 3.4. Programming the Design into an Intel FPGA 3.5. Loading the Design in the Transceiver Toolkit 3.6. Linking Hardware Resources 3.7. Identifying Transceiver Channels 3.8. Creating Transceiver Links 3.9. Running Link Tests 3.10. Controlling PMA Analog Settings 3.11. User Interface Settings Reference 3.12. Troubleshooting Common Errors 3.13. Scripting API Reference 3.14. Debugging Transceiver Links Revision History
3.1. Channel Manager x
3.1.1. Channel Display Modes
3.3. Modifying the Design to Enable Transceiver Debug x
3.3.1. Adapting an Intel FPGA Design Example 3.3.2. Stratix® V Debug System Configuration 3.3.3. Instantiating and Parameterizing Intel® Arria® 10 Debug IP cores
3.3.1. Adapting an Intel FPGA Design Example x
3.3.1.1. Modifying Stratix® V Design Examples
3.3.1.1. Modifying Stratix® V Design Examples x
3.3.1.1.1. Generating reconfig_clk from an Internal PLL
3.3.2. Stratix® V Debug System Configuration x
3.3.2.1. Bit Error Rate Test Configuration ( Stratix® V) 3.3.2.2. PRBS Signal Eye Test Configuration ( Stratix® V) 3.3.2.3. Custom Traffic Signal Eye Test Configuration ( Stratix® V) 3.3.2.4. Link Optimization Test Configuration ( Stratix® V) 3.3.2.5. PMA Analog Setting Control Configuration ( Stratix® V)
3.3.3. Instantiating and Parameterizing Intel® Arria® 10 Debug IP cores x
3.3.3.1. Debug Settings for Transceiver IP Cores
3.6. Linking Hardware Resources x
3.6.1. Linking One Design to One Device 3.6.2. Linking Two Designs to Two Devices 3.6.3. Linking One Design on Two Devices 3.6.4. Linking Designs and Devices on Separate Boards 3.6.5. Verifying Hardware Connections
3.7. Identifying Transceiver Channels x
3.7.1. Controlling Transceiver Channels
3.9. Running Link Tests x
3.9.1. Running BER Tests 3.9.2. Signal Eye Margin Testing ( Stratix® V only) 3.9.3. Running Custom Traffic Tests ( Stratix® V only) 3.9.4. Link Optimization Tests
3.9.2. Signal Eye Margin Testing ( Stratix® V only) x
3.9.2.1. Running PRBS Signal Eye Tests ( Stratix® V only)
3.9.4. Link Optimization Tests x
3.9.4.1. Running the Auto Sweep Test 3.9.4.2. Determining the Best Tap Settings
3.10. Controlling PMA Analog Settings x
3.10.1. Intel® Arria® 10 and Intel® Cyclone® 10 GX PMA Settings
3.13. Scripting API Reference x
3.13.1. Transceiver Toolkit Commands 3.13.2. Data Pattern Generator Commands 3.13.3. Data Pattern Checker Commands
4. Quick Design Debugging Using Signal Probe x
4.1. Design Flow Using Signal Probe 4.2. Scripting Support 4.3. Quick Design Debugging Using Signal Probe Revision History
4.1. Design Flow Using Signal Probe x
4.1.1. Perform a Full Compilation 4.1.2. Reserve Signal Probe Pins 4.1.3. Assign Signal Probe Sources 4.1.4. Add Registers Between Pipeline Paths and Signal Probe Pins 4.1.5. Perform a Signal Probe Compilation 4.1.6. Analyze the Results of a Signal Probe Compilation 4.1.7. What a Signal Probe Compilation Does 4.1.8. Understanding the Results of a Signal Probe Compilation
4.1.8. Understanding the Results of a Signal Probe Compilation x
4.1.8.1. Analyzing Signal Probe Routing Failures
4.2. Scripting Support x
4.2.1. Making a Signal Probe Pin 4.2.2. Deleting a Signal Probe Pin 4.2.3. Enabling a Signal Probe Pin 4.2.4. Disabling a Signal Probe Pin 4.2.5. Performing a Signal Probe Compilation 4.2.6. Reserving Signal Probe Pins 4.2.7. Adding Signal Probe Sources 4.2.8. Assigning I/O Standards 4.2.9. Adding Registers for Pipelining 4.2.10. Running Signal Probe Immediately After a Full Compilation 4.2.11. Running Signal Probe Manually 4.2.12. Enabling or Disabling All Signal Probe Routing 4.2.13. Allowing Signal Probe to Modify Fitting Results
4.2.5. Performing a Signal Probe Compilation x
4.2.5.1. Script Example
4.2.6. Reserving Signal Probe Pins x
4.2.6.1. Common Problems When Reserving a Signal Probe Pin
5. Design Debugging with the Signal Tap Logic Analyzer x
5.1. The Signal Tap Logic Analyzer 5.2. Signal Tap Logic Analyzer Task Flow Overview 5.3. Configuring the Signal Tap Logic Analyzer 5.4. Defining Triggers 5.5. Compiling the Design 5.6. Program the Target Device or Devices 5.7. Running the Signal Tap Logic Analyzer 5.8. View, Analyze, and Use Captured Data 5.9. Other Features 5.10. Design Example: Using Signal Tap Logic Analyzers 5.11. Custom Triggering Flow Application Examples 5.12. Signal Tap Scripting Support 5.13. Design Debugging with the Signal Tap Logic Analyzer Revision History
5.1. The Signal Tap Logic Analyzer x
5.1.1. Hardware and Software Requirements 5.1.2. Signal Tap Logic Analyzer Features and Benefits 5.1.3. Backward Compatibility with Previous Versions of Intel® Quartus® Prime Software
5.1.1. Hardware and Software Requirements x
5.1.1.1. Opening the Standalone Signal Tap Logic Analyzer GUI
5.2. Signal Tap Logic Analyzer Task Flow Overview x
5.2.1. Add the Signal Tap Logic Analyzer to Your Design 5.2.2. Configure the Signal Tap Logic Analyzer 5.2.3. Define Trigger Conditions 5.2.4. Compile the Design 5.2.5. Program the Target Device or Devices 5.2.6. Run the Signal Tap Logic Analyzer 5.2.7. View, Analyze, and Use Captured Data
5.3. Configuring the Signal Tap Logic Analyzer x
5.3.1. Assigning an Acquisition Clock 5.3.2. Adding Signals to the Signal Tap File 5.3.3. Adding Signals with a Plug-In 5.3.4. Adding Finite State Machine State Encoding Registers 5.3.5. Specifying Sample Depth 5.3.6. Capture Data to a Specific RAM Type 5.3.7. Select the Buffer Acquisition Mode 5.3.8. Specifying Pipeline Settings 5.3.9. Filtering Relevant Samples 5.3.10. Manage Multiple Signal Tap Files and Configurations
5.3.2. Adding Signals to the Signal Tap File x
5.3.2.1. Pre-Synthesis Signals 5.3.2.2. Post-Fit Signals 5.3.2.3. Signal Preservation 5.3.2.4. Node List Signal Use Options 5.3.2.5. Signals Unavailable for Signal Tap Debugging
5.3.2.2. Post-Fit Signals x
5.3.2.2.1. Assigning Data Signals with the Technology Map Viewer
5.3.2.4. Node List Signal Use Options x
5.3.2.4.1. Disabling and Enabling a Signal Tap Instance
5.3.4. Adding Finite State Machine State Encoding Registers x
5.3.4.1. Modify and Restore Mnemonic Tables for State Machines 5.3.4.2. Additional Considerations for State Machines in Signal Tap
5.3.7. Select the Buffer Acquisition Mode x
5.3.7.1. Non-Segmented Buffer 5.3.7.2. Segmented Buffer
5.3.8. Specifying Pipeline Settings x
5.3.8.1. Specifying Pipeline Settings from Platform Designer (Standard)
5.3.9. Filtering Relevant Samples x
5.3.9.1. Input Port Mode 5.3.9.2. Transitional Mode 5.3.9.3. Conditional Mode 5.3.9.4. Start/Stop Mode 5.3.9.5. State-Based 5.3.9.6. Showing Data Discontinuities 5.3.9.7. Disable Storage Qualifier
5.3.10. Manage Multiple Signal Tap Files and Configurations x
5.3.10.1. Data Log Pane 5.3.10.2. SOF Manager
5.4. Defining Triggers x
5.4.1. Basic Trigger Conditions 5.4.2. Comparison Trigger Conditions 5.4.3. Advanced Trigger Conditions 5.4.4. Custom Trigger HDL Object 5.4.5. Trigger Condition Flow Control 5.4.6. Specify Trigger Position 5.4.7. Power-Up Triggers 5.4.8. External Triggers
5.4.1. Basic Trigger Conditions x
5.4.1.1. Using the Basic OR Trigger Condition with Nested Groups
5.4.2. Comparison Trigger Conditions x
5.4.2.1. Specifying the Comparison Trigger Conditions
5.4.3. Advanced Trigger Conditions x
5.4.3.1. Examples of Advanced Triggering Expressions
5.4.4. Custom Trigger HDL Object x
5.4.4.1. Using the Custom Trigger HDL Object 5.4.4.2. Required Inputs and Outputs of Custom Trigger HDL Module 5.4.4.3. Custom Trigger HDL Module Properties
5.4.5. Trigger Condition Flow Control x
5.4.5.1. Sequential Triggering 5.4.5.2. State-Based Triggering 5.4.5.3. Signal Tap Trigger Flow Description Language 5.4.5.4. State-Based Storage Qualifier Feature
5.4.5.1. Sequential Triggering x
5.4.5.1.1. Configuring the Sequential Triggering Flow 5.4.5.1.2. Trigger that Skips Clock Cycles after Hitting Condition 5.4.5.1.3. Storage Qualification with Post-Fill Count Value Less than m
5.4.5.2. State-Based Triggering x
5.4.5.2.1. State-Based Triggering Flow Tab 5.4.5.2.2. Trigger Lock Mode
5.4.5.3. Signal Tap Trigger Flow Description Language x
5.4.5.3.1. <state_label> 5.4.5.3.2. <boolean_expression> 5.4.5.3.3. <action_list>
5.4.5.4. State-Based Storage Qualifier Feature x
5.4.5.4.1. Storage Qualification Feature for the State-Based Trigger Flow.
5.4.6. Specify Trigger Position x
5.4.6.1. Post-fill Count
5.4.7. Power-Up Triggers x
5.4.7.1. Enabling a Power-Up Trigger 5.4.7.2. Configuring Power-Up Trigger Conditions 5.4.7.3. Managing Signal Tap Instances with Run-Time and Power-Up Trigger Conditions
5.4.8. External Triggers x
5.4.8.1. Using the Trigger Out of One Analyzer as the Trigger In of Another Analyzer
5.5. Compiling the Design x
5.5.1. Faster Compilations with Intel® Quartus® Prime Incremental Compilation 5.5.2. Prevent Changes Requiring Recompilation 5.5.3. Verify Whether You Need to Recompile Your Project 5.5.4. Incremental Route with Rapid Recompile 5.5.5. Timing Preservation with the Signal Tap Logic Analyzer 5.5.6. Performance and Resource Considerations
5.5.1. Faster Compilations with Intel® Quartus® Prime Incremental Compilation x
5.5.1.1. Enabling Incremental Compilation for Your Design 5.5.1.2. Using Incremental Compilation with the Signal Tap Logic Analyzer
5.5.4. Incremental Route with Rapid Recompile x
5.5.4.1. Using the Incremental Route Flow 5.5.4.2. Tips to Achieve Maximum Speedup
5.5.6. Performance and Resource Considerations x
5.5.6.1. Signal Tap Logic in Critical Path 5.5.6.2. Signal Tap Logic Using Critical Resources
5.6. Program the Target Device or Devices x
5.6.1. Ensure Setting Compatibility Between .stp and .sof Files
5.7. Running the Signal Tap Logic Analyzer x
5.7.1. Runtime Reconfigurable Options 5.7.2. Signal Tap Status Messages
5.8. View, Analyze, and Use Captured Data x
5.8.1. Capturing Data Using Segmented Buffers 5.8.2. Differences in Pre-Fill Write Behavior Between Different Acquisition Modes 5.8.3. Creating Mnemonics for Bit Patterns 5.8.4. Automatic Mnemonics with a Plug-In 5.8.5. Locating a Node in the Design 5.8.6. Saving Captured Data 5.8.7. Exporting Captured Data to Other File Formats 5.8.8. Creating a Signal Tap List File
5.8.2. Differences in Pre-Fill Write Behavior Between Different Acquisition Modes x
5.8.2.1. Example
5.9. Other Features x
5.9.1. Creating Signal Tap File from Design Instances 5.9.2. Using the Signal Tap MATLAB* MEX Function to Capture Data 5.9.3. Using Signal Tap in a Lab Environment 5.9.4. Remote Debugging Using the Signal Tap Logic Analyzer 5.9.5. Using the Signal Tap Logic Analyzer in Devices with Configuration Bitstream Security 5.9.6. Monitor FPGA Resources Used by the Signal Tap Logic Analyzer
5.9.1. Creating Signal Tap File from Design Instances x
5.9.1.1. Creating a .stp File from a Design Instance
5.9.4. Remote Debugging Using the Signal Tap Logic Analyzer x
5.9.4.1. Debugging Using a Local PC and an SoC 5.9.4.2. Debugging Using a Local PC and a Remote PC
5.9.4.2. Debugging Using a Local PC and a Remote PC x
5.9.4.2.1. Equipment Setup
5.11. Custom Triggering Flow Application Examples x
5.11.1. Design Example 1: Specifying a Custom Trigger Position 5.11.2. Design Example 2: Trigger When triggercond1 Occurs Ten Times between triggercond2 and triggercond3
5.12. Signal Tap Scripting Support x
5.12.1. Signal Tap Command-Line Options 5.12.2. Data Capture from the Command Line
6. In-System Debugging Using External Logic Analyzers x
6.1. About the Intel® Quartus® Prime Logic Analyzer Interface 6.2. Choosing a Logic Analyzer 6.3. Flow for Using the LAI 6.4. Controlling the Active Bank During Runtime 6.5. Using the LAI with Incremental Compilation 6.6. LAI Core Parameters 6.7. In-System Debugging Using External Logic Analyzers Revision History
6.2. Choosing a Logic Analyzer x
6.2.1. Required Components
6.3. Flow for Using the LAI x
6.3.1. Defining Parameters for the Logic Analyzer Interface 6.3.2. Mapping the LAI File Pins to Available I/O Pins 6.3.3. Mapping Internal Signals to the LAI Banks 6.3.4. Compiling Your Intel® Quartus® Prime Project 6.3.5. Programming Your Intel-Supported Device Using the LAI
6.4. Controlling the Active Bank During Runtime x
6.4.1. Acquiring Data on Your Logic Analyzer
7. In-System Modification of Memory and Constants x
7.1. Setting Up In-System Modifiable Memories and Constants 7.2. Running the In-System Memory Content Editor 7.3. In-System Modification of Memory and Constants Revision History
7.2. Running the In-System Memory Content Editor x
7.2.1. Instance Manager 7.2.2. Editing Data Displayed in the Hex Editor Pane 7.2.3. Importing and Exporting Memory Files 7.2.4. Scripting Support 7.2.5. Programming the Device with the In-System Memory Content Editor 7.2.6. Example: Using the In-System Memory Content Editor with the Signal Tap Logic Analyzer
8. Design Debugging Using In-System Sources and Probes x
8.1. Hardware and Software Requirements 8.2. Design Flow Using the In-System Sources and Probes Editor 8.3. Compiling the Design 8.4. Running the In-System Sources and Probes Editor 8.5. Tcl interface for the In-System Sources and Probes Editor 8.6. Design Example: Dynamic PLL Reconfiguration 8.7. Design Debugging Using In-System Sources and Probes Revision History
8.2. Design Flow Using the In-System Sources and Probes Editor x
8.2.1. Instantiating the In-System Sources and Probes IP Core 8.2.2. In-System Sources and Probes IP Core Parameters
8.4. Running the In-System Sources and Probes Editor x
8.4.1. In-System Sources and Probes Editor GUI 8.4.2. Programming Your Device With JTAG Chain Configuration 8.4.3. Instance Manager 8.4.4. In-System Sources and Probes Editor Pane
8.4.4. In-System Sources and Probes Editor Pane x
8.4.4.1. Reading Probe Data 8.4.4.2. Writing Data 8.4.4.3. Organizing Data
1. System Debugging Tools Overview
2. Analyzing and Debugging Designs with System Console
3. Debugging Transceiver Links
4. Quick Design Debugging Using Signal Probe
5. Design Debugging with the Signal Tap Logic Analyzer
6. In-System Debugging Using External Logic Analyzers
7. In-System Modification of Memory and Constants
8. Design Debugging Using In-System Sources and Probes
A. Intel® Quartus® Prime Standard Edition User Guides

3.11. User Interface Settings Reference

The Transceiver Toolkit user interface contains the following settings:

Table 41.  Transceiver Toolkit Control Pane SettingsSettings in alphabetical order. All the settings appear in the Transceiver Link control pane.
Setting Description Device Families Control Pane
Alias Name you choose for the channel. All supported device families

Transmitter pane

Receiver pane
Auto Sweep status Reports the current and best tested bits, errors, bit error rate, and case count for the current Auto Sweep test. All supported device families Receiver pane
Bit error rate (BER) Reports the number of errors divided by bits tested since the last reset of the checker. All supported device families Receiver pane
Channel address Logical address number of the transceiver channel. All supported device families

Transmitter pane

Receiver pane
Data rate

Data rate of the channel that appears in the project file, or data rate the frequency detector measures.

To use the frequency detector, turn on Enable Frequency Counter in the Data Pattern Checker IP core or Data Pattern Generator IP core, regenerate the IP cores, and recompile the design.

The measured data rate depends on the Avalon® management clock frequency that appears in the project file.

If you make changes to your settings and want to sample the data rate again, click the Refresh button next to the Data rate

All supported device families

Transmitter pane

Receiver pane
DC gain Provides an equal boost to the incoming signal across the frequency spectrum. All supported device families Receiver pane
DFE mode

Decision feedback equalization (DFE) for improving signal quality.

Device Value
Stratix® V 1-5
Intel® Arria® 10 1-11

In Stratix® V devices DFE modes are Off, Manual, One-time adaptive mode and Adaptation Enabled. Adaptation Enabled mode DFE automatically tries to find the best tap values.

In Intel® Arria® 10 devices, DFE modes are Off, Manual and Adaptation Enabled. DFE in Adaptation Enabled mode automatically tries to find the best tap values.

Stratix® V

Intel® Arria® 10 		Receiver pane
Enable word aligner Forces the transceiver channel to align to the word you specify. Stratix® V Receiver pane
Equalization control

Boosts the high-frequency gain of the incoming signal to compensate for the low-pass filter effects of the physical medium. When you use this option with DFE, use DFE in Manual or Adaptation Enabled mode.

In Stratix® V devices, auto sweep supports AEQ one-time adaptation.

All supported device families Receiver pane
Equalization mode

For Intel® Arria® 10 devices, you can set Equalization Mode to Manual or Triggered.

In Stratix® V devices, Adaptive equalization (AEQ) automatically evaluates and selects the best combination of equalizer settings, and turns off Equalization Control. The one-time selection determines the best setting and stops searching. You can use AEQ for multiple, independently controlled receiver channels.

All supported device families Receiver pane
Error rate limit

Turns on or off error rate limits. Start checking after specifies the number of bits the toolkit waits before looking at the bit error rate (BER) for the next two checks.

Bit error rate achieves below sets upper bit error rate limits. If the error rate is better than the set error rate, the test ends.

Bit error rate exceeds sets lower bit error rate limits. If the error rate is worse than the set error rate, the test ends.

All supported device families Receiver pane
Generator/Checker mode

Specifies Data pattern checker or Serial bit comparator for BER tests.

If you enable Serial bit comparator the Data Pattern Generator sends the PRBS pattern, but the serial bit comparator checks the pattern.

In Bypass mode, clicking Start begins counting on the Serial bit comparator.

For BER testing:

  • Intel® Arria® 10 devices support the Data Pattern Checker and the Hard PRBS.
  • Stratix® V devices support the Data Pattern Checker and the Serial Bit Checker.
All supported device families

Transmitter pane

Receiver pane
Horizontal phase step interval Specifies the number of horizontal steps to increment when performing a sweep. Increasing the value increases the speed of the test but at a lower resolution. This option only applies to eye contour. Stratix® V

Transmitter pane

Receiver pane
Increase test range

For the selected set of controls, increases the span of tests by one unit down for the minimum, and one unit up for the maximum.

You can span either PMA Analog controls (non-DFE controls), or the DFE controls. You can quickly set up a test to check if any PMA setting combinations near your current best yields better results.

To use, right-click the Advanced panel

All supported device families Receiver pane
Inject Error Flips one bit to the output of the data pattern generator to introduce an artificial error. Stratix® V Transmitter pane
Maximum tested bits Sets the maximum number of bits tested for each test iteration. All supported device families Receiver pane
Number of bits tested Specifies the number of bits tested since the last reset of the checker. All supported device families Receiver pane
Number of error bits Specifies the number of error bits encountered since the last reset of the checker. All supported device families Receiver pane
Number of preamble beats Number of clock cycles to which the preamble word is sent before the test pattern begins. Stratix® V Transmitter pane
PLL refclk freq Channel reference clock frequency that appears in the project file, or reference clock frequency calculated from the measured data rate. All supported device families

Transmitter pane

Receiver pane
Populate with Right-click the Advanced panel to load current values on the device as a starting point, or initially load the best settings auto sweep determines. The Intel® Quartus® Prime software automatically applies the values you specify in the drop-down lists for the Transmitter settings and Receiver settings. All supported device families Receiver pane
Preamble word Word to send out if you use the preamble mode (only if you use soft PRBS Data Pattern Generator and Checker). All supported device families Transmitter pane
Pre-emphasis

This programmable module boosts high frequencies in the transmit data for each transmit buffer signal. This action counteracts possible attenuation in the transmission media.

( Stratix® V only) Using pre-emphasis can maximize the data eye opening at the far-end receiver.

All supported device families Transmitter pane
Receiver channel Specifies the name of the selected receiver channel. All supported device families Receiver pane
Refresh Button After loading the .pof file, loads fresh settings from the registers after running dynamic reconfiguration. All supported device families

Transmitter pane

Receiver pane
Reset Resets the current test. All supported device families Receiver pane
Rules Based Configuration (RBC) validity checking

Displays in red any invalid combination of settings for each list under Transmitter settings and Receiver settings, based on previous settings.

When you enable this option, the settings appear in red to indicate the current combination is invalid. This action avoids manually testing invalid settings that you cannot compile for your design, and prevents setting the device into an invalid mode for extended periods of time and potentially damaging the circuits.

All supported device families

 Receiver pane
Run length Sets coverage parameters for test runs. All supported device families

Transmitter pane

Receiver pane
RX CDR PLL status 5 Shows the receiver in lock-to-reference (LTR) mode. When in auto-mode, if data cannot be locked, this signal alternates in LTD mode if the CDR is locked to data. All supported device families Receiver pane
RX CDR data status Shows the receiver in lock-to-data (LTD) mode. When in auto-mode, if data cannot be locked, the signal stays high when locked to data and never switches. All supported device families Receiver pane
Serial loopback enabled Inserts a serial loopback before the buffers, allowing you to form a link on a transmitter and receiver pair on the same physical channel of the device. All supported device families

Transmitter pane

Receiver pane
Start Starts the pattern generator or checker on the channel to verify incoming data. All supported device families

Transmitter pane

Receiver pane
Stop Stops generating patterns and testing the channel. All supported device families

Transmitter pane

Receiver pane
Target bit error rate Finds the contour edge of the bit error rate that you select. This option only applies to eye contour mode. Stratix® V

Transmitter pane

Receiver pane
Test pattern Test pattern sent by the transmitter channel.

The Data Pattern Checker self-aligns both high and low frequency patterns. Use Bypass mode to send user-design data.

Device Family Test Patterns Available
Stratix® V PRBS7, PRBS15, PRBS23, PRBS31, LowFrequency, HighFrequency, and Bypass mode.
Intel® Arria® 10 PRBS9, PRBS15, PRBS23, and PRBS31.
All supported device families

Transmitter pane

Receiver pane
Time limit Specifies the time limit unit and value to have a maximum bounds time limit for each test iteration. All supported device families Receiver
Transmitter channel Specifies the name of the selected transmitter channel. All supported device families Transmitter pane
TX/CMU PLL status Specifies whether the transmitter channel PLL is locked to the reference clock. All supported device families Transmitter pane
Use preamble upon start If turned on, sends the preamble word before the test pattern. If turned off, starts sending the test pattern immediately. All supported device families Transmitter pane
Vertical phase step interval Specify the number of vertical steps to increment when performing a sweep. Increasing the value increases the speed of the test but at a lower resolution. This option only applies to the eye contour. Stratix® V

Transmitter pane

Receiver pane
VOD control Programmable transmitter differential output voltage. All supported device families Transmitter pane
Related Information
5 For Stratix® V devices, the Phase Frequency Detector (PFD) is inactive in LTD mode. The rx_is_lockedtoref status signal turns on and off randomly, and is not significant in LTD mode.
Level Two Title