Visible to Intel only — GUID: mwh1410384938911
Ixiasoft
Visible to Intel only — GUID: mwh1410384938911
Ixiasoft
7.2.6. Example: Using the In-System Memory Content Editor with the Signal Tap Logic Analyzer
Scenario: After completing your FPGA design, you find that the characteristics of your FIR filter design are not as expected.
- To locate the source of the problem, change all your FIR filter coefficients to be in-system modifiable and instantiate the Signal Tap Logic Analyzer.
- Using the Signal Tap Logic Analyzer to tap and trigger on internal design nodes, you find the FIR filter to be functioning outside of the expected cutoff frequency.
- Using the In-System Memory Content Editor, you check the correctness of the FIR filter coefficients. Upon reading each coefficient, you discover that one of the coefficients is incorrect.
- Because your coefficients are in-system modifiable, you update the coefficients with the correct data with the In-System Memory Content Editor.
In this scenario, you can quickly locate the source of the problem using both the In-System Memory Content Editor and the Signal Tap Logic Analyzer. You can also verify the functionality of your device by changing the coefficient values before modifying the design source files.
You can also modify the coefficients with the In-System Memory Content Editor to vary the characteristics of the FIR filter, for example, filter attenuation, transition bandwidth, cut-off frequency, and windowing function.