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1.2.1. Functional Description for the Programmed Input/Output (PIO) Design Example
1.2.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example
1.2.3. Functional Description for the Performance Design Example
1.2.4. Functional Description for the Performance Design Example for TL Bypass Mode
1.2.5. Hardware and Software Requirements
2.4.5.1. ebfm_barwr Procedure
2.4.5.2. ebfm_barwr_imm Procedure
2.4.5.3. ebfm_barrd_wait Procedure
2.4.5.4. ebfm_barrd_nowt Procedure
2.4.5.5. ebfm_cfgwr_imm_wait Procedure
2.4.5.6. ebfm_cfgwr_imm_nowt Procedure
2.4.5.7. ebfm_cfgrd_wait Procedure
2.4.5.8. ebfm_cfgrd_nowt Procedure
2.4.5.9. BFM Configuration Procedures
2.4.5.10. BFM Shared Memory Access Procedures
2.4.5.11. BFM Log and Message Procedures
2.4.5.12. Verilog HDL Formatting Functions
2.4.5.11.1. ebfm_display Verilog HDL Function
2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function
2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task
2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task
2.4.5.11.5. ebfm_log_open Verilog HDL Function
2.4.5.11.6. ebfm_log_close Verilog HDL Function
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2.3.1.1. Siemens EDA QuestaSim* Simulator
Perform the following steps:
- Change to the simulation working directory: cd <my_design>/pcie_ed_tb/pcie_ed_tb/sim/mentor.
- Invoke vsim, which brings up a console window where you can run the next commands: Type vsim
- set TOP_LEVEL_NAME "pcie_ed_tb.pcie_ed_tb"
- do msim_setup.tcl
- ld_debug
- run -all
A successful simulation includes the following message: "Simulation stopped due to successful completion!"
Note: When running simulations under Windows* OS, if your project path is too long, you may encounter access errors to the design files. To avoid this, shorten your project path as much as possible. The longest path for any design file should be less than 189 characters.