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1.2.1. Functional Description for the Programmed Input/Output (PIO) Design Example
1.2.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example
1.2.3. Functional Description for the Performance Design Example
1.2.4. Functional Description for the Performance Design Example for TL Bypass Mode
1.2.5. Hardware and Software Requirements
2.4.5.1. ebfm_barwr Procedure
2.4.5.2. ebfm_barwr_imm Procedure
2.4.5.3. ebfm_barrd_wait Procedure
2.4.5.4. ebfm_barrd_nowt Procedure
2.4.5.5. ebfm_cfgwr_imm_wait Procedure
2.4.5.6. ebfm_cfgwr_imm_nowt Procedure
2.4.5.7. ebfm_cfgrd_wait Procedure
2.4.5.8. ebfm_cfgrd_nowt Procedure
2.4.5.9. BFM Configuration Procedures
2.4.5.10. BFM Shared Memory Access Procedures
2.4.5.11. BFM Log and Message Procedures
2.4.5.12. Verilog HDL Formatting Functions
2.4.5.11.1. ebfm_display Verilog HDL Function
2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function
2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task
2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task
2.4.5.11.5. ebfm_log_open Verilog HDL Function
2.4.5.11.6. ebfm_log_close Verilog HDL Function
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2.7.1. Running the PIO Design Example
- Navigate to ./software/user/example under the design example directory.
- Compile the design example application:
$ make
- Run the test:
$ sudo ./intel_fpga_pcie_link_test
You can run the Intel® FPGA IP PCIe* link test in manual or automatic mode. Choose from:- In automatic mode, the application automatically selects the device. The test selects the Intel PCIe* device with the lowest BDF by matching the Vendor ID. The test also selects the lowest available BAR.
- In manual mode, the test queries you for the bus, device, and function number and BAR.
For the Agilex™ 7 Development Kit, you can determine the BDF by typing the following command:
$ lspci -d 1172:
- Here are sample transcripts for automatic and manual modes:
Automatic mode:
Intel FPGA PCIe Link Test - Automatic Mode Version 2.0 0: Automatically select a device 1: Manually select a device *************************************************** >0 Opened a handle to BAR 0 of a device with BDF 0x3800 *************************************************** 0: Link test - 100 writes and reads 1: Write memory space 2: Read memory space 3: Write configuration space 4: Read configuration space 5: Change BAR for PIO 6: Change device 7: Quit program *************************************************** > 0 Doing 100 writes and 100 reads . . Number of write errors: 0 Number of read errors: 0 Number of DWORD mismatches: 0
Manual mode:
Intel FPGA PCIe Link Test Version 2.0 0: Automatically select a device 1: Manually select a device **************************************************** > 1 Enter bus number, in hex: > 4b Enter device number, in hex: > 0 BDF is 0x4b00 B:D.F, in hex, is 4b:0.0 Enter BAR number (-1 for none): > 0 Opened a handle to BAR 0 of a device with BDF 0x4b00