R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 7/08/2024
Public
Document Table of Contents

1.2. Overview of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express

The following table presents an overview of the design examples supported by the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express.

Table 2.  Design Examples Supported by the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
Design Example Hard IP Mode Simulators Supported Development Kits Supported
PIO Gen5 1x16 1024-bit Endpoint VCS* , VCS* MX, Siemens* EDA QuestaSim* , Xcelium* 1
Note: Simulation support is not available for Gen3 and Gen4 in this release of Quartus® Prime.
Agilex™ 7 I-Series FPGA Development Kit ES 2
Gen4 1x16 1024-bit Endpoint
Gen3 1x16 1024-bit Endpoint
Gen5 2x8 512-bit Endpoint
Gen4 2x8 512-bit Endpoint
Gen3 2x8 512-bit Endpoint
SR-IOV Gen5 1x16 1024-bit Endpoint VCS* , VCS* MX, Siemens* EDA QuestaSim* , Xcelium* 1 Agilex™ 7 I-Series FPGA Development Kit ES 2
Performance Gen5 1x16 1024-bit Endpoint

Simulation for the Gen5 1x16 1024-bit Performance design example is supported.

Simulation is not supported for the Gen5 2x8 512-bit Performance design example.

Agilex™ 7 I-Series FPGA Development Kit ES 2
Performance Transaction Layer (TL) Bypass Gen5 1x16 1024-bit TL Bypass

Simulation for the Gen5 1x16 1024-bit Performance design example for TL Bypass mode is not supported currently.

Agilex™ 7 I-Series FPGA Development Kit ES 2
1 Xcelium* simulator support is only available in devices with the following OPN numbers: AGIx027R29AxxxxR3, AGIx027R29AxxxxR2, AGIx027R29BxxxxR3, AGIx023R18AxxxxR0, AGIx041R29DxxxxR0, AGIx041R29DxxxxR1, AGMx039R47AxxR0. For more details on OPN decoding, refer to the Agilex™ 7 FPGAs and SoCs Device Overview
2 For more information, refer to the Agilex™ 7 I-Series FPGA Development Kit