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1.2.1. Functional Description for the Programmed Input/Output (PIO) Design Example
1.2.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example
1.2.3. Functional Description for the Performance Design Example
1.2.4. Functional Description for the Performance Design Example for TL Bypass Mode
1.2.5. Hardware and Software Requirements
2.4.5.1. ebfm_barwr Procedure
2.4.5.2. ebfm_barwr_imm Procedure
2.4.5.3. ebfm_barrd_wait Procedure
2.4.5.4. ebfm_barrd_nowt Procedure
2.4.5.5. ebfm_cfgwr_imm_wait Procedure
2.4.5.6. ebfm_cfgwr_imm_nowt Procedure
2.4.5.7. ebfm_cfgrd_wait Procedure
2.4.5.8. ebfm_cfgrd_nowt Procedure
2.4.5.9. BFM Configuration Procedures
2.4.5.10. BFM Shared Memory Access Procedures
2.4.5.11. BFM Log and Message Procedures
2.4.5.12. Verilog HDL Formatting Functions
2.4.5.11.1. ebfm_display Verilog HDL Function
2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function
2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task
2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task
2.4.5.11.5. ebfm_log_open Verilog HDL Function
2.4.5.11.6. ebfm_log_close Verilog HDL Function
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Ixiasoft
1.2.1.1.2. Credit Distribution
Based on the available FIFO depth, the available credit is distributed as shown below.
Credit Type | Credit Initialization | ||
---|---|---|---|
Header Type | Posted | Non-Posted | Completion |
Header Credit | 11 | 11 | 10 |
Data Credit | 85 | 85 | 85 |
Note: Each 16 bytes of data consume one credit.