Advanced SEU Detection Intel® FPGA IP User Guide

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ID 683542
Date 11/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Advanced SEU Detection Intel® FPGA IP Overview 2. Advanced SEU Detection Intel® FPGA IP Functional Description 3. Using the Advanced SEU Detection Intel® FPGA IP 4. SEU Mitigation on CRAM Array 5. Advanced SEU Detection Intel® FPGA IP User Guide Archives 6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide
2. Advanced SEU Detection Intel® FPGA IP Functional Description x
2.1. On-Chip Lookup Sensitivity Processing 2.2. Off-Chip Lookup Sensitivity Processing
2.1. On-Chip Lookup Sensitivity Processing x
2.1.1. On-Chip Sensitivity Processor 2.1.2. On-Chip Processing Signals
2.2. Off-Chip Lookup Sensitivity Processing x
2.2.1. Off-Chip Lookup Sensitivity Processing Operation Flow 2.2.2. External Sensitivity Processor 2.2.3. Off-Chip Processing Signals 2.2.4. SMH Lookup
2.2.4. SMH Lookup x
2.2.4.1. SMH File Types
3. Using the Advanced SEU Detection Intel® FPGA IP x
3.1. Customizing and Generating IP Cores 3.2. Advanced SEU Detection IP Core Parameters
3.1. Customizing and Generating IP Cores x
3.1.1. IP Catalog and Parameter Editor 3.1.2. The Parameter Editor 3.1.3. Specifying IP Core Parameters and Options
3.1.3. Specifying IP Core Parameters and Options x
3.1.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
4. SEU Mitigation on CRAM Array x
4.1. Enabling the Advanced SEU Detection Feature in the Quartus® Prime Software 4.2. Hierarchy Tagging 4.3. Sensitivity Map Header File Lookup
4.2. Hierarchy Tagging x
4.2.1. Using Partitions to Specify Logic Sensitivity ID
4.3. Sensitivity Map Header File Lookup x
4.3.1. Programming Sensitivity Map Header File into Memory 4.3.2. Performing a Lookup for SMH Revision 1 ( Stratix® IV and Arria® II) 4.3.3. Performing a Lookup for SMH Revision 2 ( Stratix® V, Arria® V, and Cyclone® V Devices) 4.3.4. Performing a Lookup for SMH Revision 3 ( Arria® 10 and Cyclone® 10 GX Devices)
1. Advanced SEU Detection Intel® FPGA IP Overview
2. Advanced SEU Detection Intel® FPGA IP Functional Description
3. Using the Advanced SEU Detection Intel® FPGA IP
4. SEU Mitigation on CRAM Array
5. Advanced SEU Detection Intel® FPGA IP User Guide Archives
6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide

2.2. Off-Chip Lookup Sensitivity Processing

The Advanced SEU Detection IP core analyzes the content of the error detection block’s EMR and presents information to a system processor. The processor determines whether the failure affects the device operation. The system processor implements the algorithm to perform a lookup against the .smh.

The off-chip lookup sensitivity processing consists of two components:

  • Design logic to interpret content of the EMR of the CRC block and present the information to a processor interface.
  • Cache to store off-loaded content of the EMR.
Figure 3. System Overview for Off-Chip Lookup Sensitivity Processing

The EMR processing unit analyzes the content of EMR offloaded from the CRC block by the EMR Unloader IP core upon an SEU. The EMR processing unit writes each unique EMR value into cache, until the cache is full. When the cache is full, it asserts a cache overflow flag to the system interface.

For each new value written into cache, the EMR processing unit asserts an interrupt to the processor. The system processor reads the EMR value and performs a lookup against the .smh to determine the criticality of a CRAM location. After the system processor services the interrupt, the EMR processing unit advances the cache line and generates additional interrupt assertions, provided that there is an EMR value in cache that has not been processed.

After SMH lookup, the system processor determines the required corrective response.


Section Content
Off-Chip Lookup Sensitivity Processing Operation Flow
External Sensitivity Processor
Off-Chip Processing Signals
SMH Lookup

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