Advanced SEU Detection Intel® FPGA IP User Guide

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ID 683542
Date 11/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Advanced SEU Detection Intel® FPGA IP Overview 2. Advanced SEU Detection Intel® FPGA IP Functional Description 3. Using the Advanced SEU Detection Intel® FPGA IP 4. SEU Mitigation on CRAM Array 5. Advanced SEU Detection Intel® FPGA IP User Guide Archives 6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide
2. Advanced SEU Detection Intel® FPGA IP Functional Description x
2.1. On-Chip Lookup Sensitivity Processing 2.2. Off-Chip Lookup Sensitivity Processing
2.1. On-Chip Lookup Sensitivity Processing x
2.1.1. On-Chip Sensitivity Processor 2.1.2. On-Chip Processing Signals
2.2. Off-Chip Lookup Sensitivity Processing x
2.2.1. Off-Chip Lookup Sensitivity Processing Operation Flow 2.2.2. External Sensitivity Processor 2.2.3. Off-Chip Processing Signals 2.2.4. SMH Lookup
2.2.4. SMH Lookup x
2.2.4.1. SMH File Types
3. Using the Advanced SEU Detection Intel® FPGA IP x
3.1. Customizing and Generating IP Cores 3.2. Advanced SEU Detection IP Core Parameters
3.1. Customizing and Generating IP Cores x
3.1.1. IP Catalog and Parameter Editor 3.1.2. The Parameter Editor 3.1.3. Specifying IP Core Parameters and Options
3.1.3. Specifying IP Core Parameters and Options x
3.1.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
4. SEU Mitigation on CRAM Array x
4.1. Enabling the Advanced SEU Detection Feature in the Quartus® Prime Software 4.2. Hierarchy Tagging 4.3. Sensitivity Map Header File Lookup
4.2. Hierarchy Tagging x
4.2.1. Using Partitions to Specify Logic Sensitivity ID
4.3. Sensitivity Map Header File Lookup x
4.3.1. Programming Sensitivity Map Header File into Memory 4.3.2. Performing a Lookup for SMH Revision 1 ( Stratix® IV and Arria® II) 4.3.3. Performing a Lookup for SMH Revision 2 ( Stratix® V, Arria® V, and Cyclone® V Devices) 4.3.4. Performing a Lookup for SMH Revision 3 ( Arria® 10 and Cyclone® 10 GX Devices)
1. Advanced SEU Detection Intel® FPGA IP Overview
2. Advanced SEU Detection Intel® FPGA IP Functional Description
3. Using the Advanced SEU Detection Intel® FPGA IP
4. SEU Mitigation on CRAM Array
5. Advanced SEU Detection Intel® FPGA IP User Guide Archives
6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide

3.1.3. Specifying IP Core Parameters and Options

Follow these steps to specify IP core parameters and options.
  1. In the Platform Designer IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.
  2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target FPGA device family and output file HDL preference. Click OK.
  3. Specify parameters and options for your IP variation:
    • Optionally select preset parameter values. Presets specify all initial parameter values for specific applications (where provided).
    • Specify parameters defining the IP core functionality, port configurations, and device-specific features.
    • Specify options for generation of a timing netlist, simulation model, testbench, or example design (where applicable).
    • Specify options for processing the IP core files in other EDA tools.
  4. Click Finish to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level .qsys IP variation file and HDL files for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example design for hardware testing.
  5. To generate a simulation testbench, click Generate > Generate Testbench System. Generate Testbench System is not available for some IP cores that do not provide a simulation testbench.
  6. To generate a top-level HDL example for hardware verification, click Generate > HDL Example. Generate > HDL Example is not available for some IP cores.

The top-level IP variation is added to the current Quartus® Prime project. Click Project > Add/Remove Files in Project to manually add a .qsys ( Quartus® Prime Standard Edition) or .ip ( Quartus® Prime Pro Edition) file to a project. Make appropriate pin assignments to connect ports.


Section Content
IP Core Generation Output ( Quartus Prime Pro Edition)

Level Two Title