Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide
ID
683517
Date
12/01/2021
Public
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: fbf1635458049775
Ixiasoft
Note: All addresses in the programming sequence need to shift by a particular offset:
- In case of x8, shift by 5 bits
- In case of x16, shift by 6 bits
- Allocate DMA-able memory in the host system.
- Program the base address with the read_map_table with the physical address of the host memory.
- Set the read address register with the offset in block where Traffic checker needs to read and verify the data.
- Set how many number of bursts BAS should read from host memory in the READ_COUNT register.
- Set the enable bit to start traffic checker.