Visible to Intel only — GUID: ptu1634430263388
Ixiasoft
2.7.1. Traffic Generator and checker Example Design Register Map
The control and status registers of the traffic generator and checker are byte addresses and must be Avalon-MM word aligned (for example, bits [5:0] are assumed to be set to 0 for x16 (OR) bits [4:0] are assumed to be set to 0 for x8).
Bit[63:0] | Name | R/W | Default | Description |
---|---|---|---|---|
[63:32] | rsvd | Reserved | ||
[31:0] | RAdd | R/W | 0 | This register contains the base addresses that the Traffic Checker reads from. |
Bit[63:0] | Name | R/W | Default | Description |
---|---|---|---|---|
[63:32] | rsvd | Reserved | ||
[31] | Mode | R/W | 0 | 0: Fixed no of transfers 1: non-stop transfers |
[30:12] | rsvd | Reserved | ||
[11:0] | RCnt | R/W | 0 | Write to the RCnt registers to specify the number of transfers to execute. Reading from one of these registers returns the number of transfers that have occurred since it was last read. |
Bit[63:0] | Name | R/W | Default | Description |
---|---|---|---|---|
[63:12] | rsvd | Reserved | ||
[11:0] | RErr | ROC | 0 | Reading the RErr register returns the number of errors detected since the register was last read. A maximum of one error is counted per clock cycle. |
Bit[63:0] | Name | R/W | Default | Description |
---|---|---|---|---|
[63:32] | rsvd | Reserved | ||
[31] | enable | R/W | 0 | 0: stop 1: start |
[30:8] | rsvd | Reserved | ||
[7:0] | transfer_size | 0 | This register configures the burst length per transfer (ideal value for x16 is 8 & x8 is 16). Zero is not a legal value. |
Bit[63:0] | Name | R/W | Default | Description |
---|---|---|---|---|
[63:32] | rsvd | Reserved | ||
[31:0] | WAdd | R/W | 0 | This register contains the base addresses that the Traffic Generator writes to. |
Bit[63:0] | Name | R/W | Default | Description |
---|---|---|---|---|
[63:32] | rsvd | Reserved | ||
[31] | Mode | R/W | 0 | 0: Fixed no of transfers 1: non-stop transfers |
[30:12] | rsvd | Reserved | ||
[11:0] | WCnt | R/W | 0 | Write to the WCnt registers to specify the number of transfers to execute. Reading from one of these registers returns the number of transfers that have occurred since it was last read. |
Bit[63:0] | Name | R/W | Default | Description |
---|---|---|---|---|
[63:12] | rsvd | Reserved | ||
[11:0] | WErr | ROC | 0 | Reserved (Write error detection not available yet). Because the write error detection feature is not available yet, you cannot get a valid number of errors by reading the WErr register. |
Bit[63:0] | Name | R/W | Default | Description |
---|---|---|---|---|
[63:32] | rsvd | Reserved | ||
[31] | enable | R/W | 0 | 0: stop 1: start |
[30:8] | rsvd | Reserved | ||
[7:0] | transfer_size | 0 | This register configures the burst length per transfer (ideal value for x16 is 8 & x8 is 16). Zero is not a legal value. |
Bit[63:0] | Name | R/W | Default | Description |
---|---|---|---|---|
[63:0] | raDM | R/W | 0 | This register contains the Traffic Checker address mapping table that maps thirty-two 1 MB regions of the Avalon-MM memory space into thirty-two 1 MB regions of the PCIe address space. The module occupies only 32MB of the Avalon-MM address space, and only needs a 25-bit wide address bus, leaving space for other Avalon-MM slaves. |
Bit[63:0] | Name | R/W | Default | Description |
---|---|---|---|---|
[63:0] | WAdm | R/W | 0 | This register contains the Traffic Generator address mapping table that maps thirty-two 1 MB regions of the Avalon-MM memory space into thirty-two 1 MB regions of the PCIe address space. The module occupies only 32MB of the Avalon-MM address space, and only needs a 25-bit wide address bus, leaving space for other Avalon-MM slaves. |