P-Tile Intel® FPGA IP for PCI Express* IP Core Release Notes

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ID 683508
Date 7/08/2024
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1. P-Tile IP for PCI Express IP Core Release Notes
1. P-Tile IP for PCI Express IP Core Release Notes x
1.1. P-Tile IP for PCI Express IP Cores v9.1.2 1.2. P-Tile IP for PCI Express IP Cores v9.1.1 1.3. P-Tile IP for PCI Express IP Cores v9.1.0 1.4. P-Tile IP for PCI Express IP Cores v9.0.3 1.5. P-Tile IP for PCI Express IP Cores v9.0.2 1.6. P-Tile IP for PCI Express IP Cores v9.0.1 1.7. P-Tile IP for PCI Express IP Cores v9.0.0 1.8. P-Tile IP for PCI Express IP Cores v8.3.0 1.9. P-Tile IP for PCI Express IP Cores v8.1.0 1.10. P-Tile IP for PCI Express IP Cores v8.0.0 1.11. P-Tile IP for PCI Express IP Cores v7.0.0 1.12. P-Tile IP for PCI Express IP Cores v6.0.0 1.13. P-Tile IP for PCI Express IP Cores v5.0.0 1.14. P-Tile IP for PCI Express IP Cores v4.0.0 1.15. P-Tile IP for PCI Express IP Cores v4.0.0 1.16. P-Tile IP for PCI Express IP Cores v3.1.0 1.17. P-Tile IP for PCI Express IP Cores v3.0.0 1.18. P-Tile IP for PCI Express IP Cores v2.0.0 1.19. P-Tile IP for PCI Express IP Cores v1.1.0 1.20. P-Tile IP for PCI Express IP Cores v19.3 1.21. P-Tile IP for PCI Express IP Cores v19.2 1.22. P-Tile IPs for PCI Express User Guide Archives
1. P-Tile IP for PCI Express IP Core Release Notes

1.3. P-Tile IP for PCI Express IP Cores v9.1.0

The IP version (X.Y.Z) number may change from one Quartus® Prime software version to another. A change in:
  • X indicates a major revision of the IP. If you update your Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 7.  v9.1.0 2023.12.04
Quartus® Prime Version Description Impact
23.4 app_init_rst_i is supported for TLP Bypass Downstream mode. The app_init_rst_i port is exposed when the TLP Bypass Downstream mode is selected and the Power Management Interface is enabled. This port allows the Application layer to send hot reset requests to downstream devices. For additional details, refer to the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide.
Margin mask information based on the 3rd Generation Intel® Xeon® Scalable Processor Platform has been provided. The margin mask information provided is subject to change as your system design may be different from the design of the validation system of Intel. For additional details, refer to the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide.
Table 8.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 450 MHz 450 MHz 350 MHz
Gen4 x8 256-bit S C T H N/A N/A S C T H N/A N/A 450 MHz 450 MHz 350 MHz
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 450 MHz 450 MHz 350 MHz
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8 256-bit S C T H N/A N/A S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 9.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3 -4
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 500 MHz 500 MHz 450 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 500 MHz 500 MHz 450 MHz 350 MHz
Gen4 x8 256-bit S C T H N/A N/A S C T H N/A N/A 500 MHz 500 MHz 450 MHz 350 MHz
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 500 MHz 500 MHz 450 MHz 350 MHz
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
Gen3 x8 256-bit S C T H N/A N/A S C T H N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
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