P-Tile Intel® FPGA IP for PCI Express* IP Core Release Notes

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ID 683508
Date 7/08/2024
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1. P-Tile IP for PCI Express IP Core Release Notes
1. P-Tile IP for PCI Express IP Core Release Notes x
1.1. P-Tile IP for PCI Express IP Cores v9.1.2 1.2. P-Tile IP for PCI Express IP Cores v9.1.1 1.3. P-Tile IP for PCI Express IP Cores v9.1.0 1.4. P-Tile IP for PCI Express IP Cores v9.0.3 1.5. P-Tile IP for PCI Express IP Cores v9.0.2 1.6. P-Tile IP for PCI Express IP Cores v9.0.1 1.7. P-Tile IP for PCI Express IP Cores v9.0.0 1.8. P-Tile IP for PCI Express IP Cores v8.3.0 1.9. P-Tile IP for PCI Express IP Cores v8.1.0 1.10. P-Tile IP for PCI Express IP Cores v8.0.0 1.11. P-Tile IP for PCI Express IP Cores v7.0.0 1.12. P-Tile IP for PCI Express IP Cores v6.0.0 1.13. P-Tile IP for PCI Express IP Cores v5.0.0 1.14. P-Tile IP for PCI Express IP Cores v4.0.0 1.15. P-Tile IP for PCI Express IP Cores v4.0.0 1.16. P-Tile IP for PCI Express IP Cores v3.1.0 1.17. P-Tile IP for PCI Express IP Cores v3.0.0 1.18. P-Tile IP for PCI Express IP Cores v2.0.0 1.19. P-Tile IP for PCI Express IP Cores v1.1.0 1.20. P-Tile IP for PCI Express IP Cores v19.3 1.21. P-Tile IP for PCI Express IP Cores v19.2 1.22. P-Tile IPs for PCI Express User Guide Archives
1. P-Tile IP for PCI Express IP Core Release Notes

1.19. P-Tile IP for PCI Express IP Cores v1.1.0

IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IPs have a new IP versioning scheme.

The IP version (X.Y.Z) number may change from one Quartus® Prime software version to another. A change in:
  • X indicates a major revision of the IP. If you update your Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 65.  v1.1.0 2019.12.16
Quartus® Prime Version Description Impact
19.4 The VirtIO feature still has timing issues in this release of Quartus® Prime. Only compilation and simulation are supported for the VirtIO feature in this release.
An SR-IOV design example has been added for the P-Tile Avalon-ST IP for PCIe. This design example supports Gen3 x16 and Gen4 x16 Endpoint configurations.
No P-Tile IP upgrade is supported in the 19.4 release of Quartus® Prime. Users cannot upgrade a 19.3 P-Tile Avalon-ST or Avalon-MM IP to a 19.4 version.
The P-Tile Avalon-MM IP for PCIe does not support design example simulation in this release. The P-Tile Avalon-MM IP for PCIe may support design example simulation in a future release of Quartus® Prime.
A high-bandwidth Adapter has been introduced for the P-Tile Avalon Streaming IP. This Adapter allows the application logic to run Gen4 x8 and Gen4 x4 configurations with an application clock frequency of 250 MHz by doubling the Avalon Streaming data bus width. The Adapter is enabled automatically by Quartus® Prime when either the 512-bit Gen4 x8 or 256-bit Gen4 x4 configuration is selected.
The P-Tile Avalon Streaming IP for PCI Express does not support parity protection for the RX and TX Avalon Streaming interfaces in this release of Quartus® Prime. Parity protection for the RX and TX Avalon Streaming interfaces will be supported in a future release of Quartus® Prime.
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