P-Tile Intel® FPGA IPs for PCI Express* IP Cores Release Notes

Download PDF
ID 683508
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. P-Tile IPs for PCI Express IP Core Release Notes
1. P-Tile IPs for PCI Express IP Core Release Notes x
1.1. P-Tile IP for PCI Express IP Cores v9.2.0 1.2. P-Tile IP for PCI Express IP Cores v9.1.2 1.3. P-Tile IP for PCI Express IP Cores v9.1.1 1.4. P-Tile IP for PCI Express IP Cores v9.1.0 1.5. P-Tile IP for PCI Express IP Cores v9.0.3 1.6. P-Tile IP for PCI Express IP Cores v9.0.2 1.7. P-Tile IP for PCI Express IP Cores v9.0.1 1.8. P-Tile IP for PCI Express IP Cores v9.0.0 1.9. P-Tile IP for PCI Express IP Cores v8.3.0 1.10. P-Tile IP for PCI Express IP Cores v8.1.0 1.11. P-Tile IP for PCI Express IP Cores v8.0.0 1.12. P-Tile IP for PCI Express IP Cores v7.0.0 1.13. P-Tile IP for PCI Express IP Cores v6.0.0 1.14. P-Tile IP for PCI Express IP Cores v5.0.0 1.15. P-Tile IP for PCI Express IP Cores v4.0.0 1.16. P-Tile IP for PCI Express IP Cores v4.0.0 1.17. P-Tile IP for PCI Express IP Cores v3.1.0 1.18. P-Tile IP for PCI Express IP Cores v3.0.0 1.19. P-Tile IP for PCI Express IP Cores v2.0.0 1.20. P-Tile IP for PCI Express IP Cores v1.1.0 1.21. P-Tile IP for PCI Express IP Cores v19.3 1.22. P-Tile IP for PCI Express IP Cores v19.2 1.23. P-Tile IPs for PCI Express User Guide Archives
1. P-Tile IPs for PCI Express IP Core Release Notes

1.9. P-Tile IP for PCI Express IP Cores v8.3.0

Table 25.  v8.3.0 2022.09.26
Quartus® Prime Version Description Impact
22.3 Added support for Independent cold and warm reset operations for the ports in the x8x8 Endpoint and x8x8 TLP Bypass UP/UP modes.

Each port in the bifurcated x8x8 mode can be reset independently of the other port. The new reset signals (p#_warm_perst_n_i, p#_cold_perst_n_i) are exported to the top-level block symbol when independent resets are enabled.

Customer designs from 22.2 (IP version 8.1.0) will require an IP upgrade in 22.3 (IP version 8.3.0).

For the P-Tile Avalon Streaming IP, you must replace the p#_pld_clrpcs_n_i signal with p#_warm_perst_n_i or p#_cold_perst_n_i when your design from 22.2 (IP version 8.1.0) goes through an IP upgrade in 22.3 (IP version 8.3.0) . These new reset signals were introduced in Quartus® Prime Pro Edition from the 22.3 release onward.

Fixed the initialization Debug Toolkit issue with the Stratix® 10 DX device family.

No impact on the user interfaces.

Fixed the issue with the p#_reset_status_n port of the P-Tile Avalon Streaming IP for PCI Express.

The IP can disable and enable both refclk0 and refclk1 across cold resets in Quartus® Prime Pro Edition from the 22.3 release onward.
Added support for refclk1 being unconnected or disabled in Gen3 and Gen4 1x8 or 2x8 modes. The IP now supports refclk1 being unconnected when Port 1 is not used in 1x8 and 2x8 modes.This feature is available in Quartus® Prime Pro Edition from the 22.3 release onward.
Table 26.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 450 MHz 450 MHz 350 MHz
Gen4 x8 256-bit S C T H N/A N/A S C T H N/A N/A 450 MHz 450 MHz 350 MHz
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 450 MHz 450 MHz 350 MHz
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8 256-bit S C T H N/A N/A S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 27.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3 -4
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 500 MHz 500 MHz 450 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 500 MHz 500 MHz 450 MHz 350 MHz
Gen4 x8 256-bit S C T H N/A N/A S C T H N/A N/A 500 MHz 500 MHz 450 MHz 350 MHz
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 500 MHz 500 MHz 450 MHz 350 MHz
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
Gen3 x8 256-bit S C T H N/A N/A S C T H N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
Level Two Title