P-Tile Intel® FPGA IP for PCI Express* IP Core Release Notes

Download PDF
ID 683508
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. P-Tile IP for PCI Express IP Core Release Notes
1. P-Tile IP for PCI Express IP Core Release Notes x
1.1. P-Tile IP for PCI Express IP Cores v9.1.2 1.2. P-Tile IP for PCI Express IP Cores v9.1.1 1.3. P-Tile IP for PCI Express IP Cores v9.1.0 1.4. P-Tile IP for PCI Express IP Cores v9.0.3 1.5. P-Tile IP for PCI Express IP Cores v9.0.2 1.6. P-Tile IP for PCI Express IP Cores v9.0.1 1.7. P-Tile IP for PCI Express IP Cores v9.0.0 1.8. P-Tile IP for PCI Express IP Cores v8.3.0 1.9. P-Tile IP for PCI Express IP Cores v8.1.0 1.10. P-Tile IP for PCI Express IP Cores v8.0.0 1.11. P-Tile IP for PCI Express IP Cores v7.0.0 1.12. P-Tile IP for PCI Express IP Cores v6.0.0 1.13. P-Tile IP for PCI Express IP Cores v5.0.0 1.14. P-Tile IP for PCI Express IP Cores v4.0.0 1.15. P-Tile IP for PCI Express IP Cores v4.0.0 1.16. P-Tile IP for PCI Express IP Cores v3.1.0 1.17. P-Tile IP for PCI Express IP Cores v3.0.0 1.18. P-Tile IP for PCI Express IP Cores v2.0.0 1.19. P-Tile IP for PCI Express IP Cores v1.1.0 1.20. P-Tile IP for PCI Express IP Cores v19.3 1.21. P-Tile IP for PCI Express IP Cores v19.2 1.22. P-Tile IPs for PCI Express User Guide Archives
1. P-Tile IP for PCI Express IP Core Release Notes

1.17. P-Tile IP for PCI Express IP Cores v3.0.0

IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IPs have a new IP versioning scheme.

The IP version (X.Y.Z) number may change from one Quartus® Prime software version to another. A change in:
  • X indicates a major revision of the IP. If you update your Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 55.  v3.0.0 2020.07.10
Quartus® Prime Version Description Impact
20.2 The VirtIO feature has timing issues in this release of Quartus® Prime. Only compilation and simulation are supported for the VirtIO feature in this release.
The Eye Plot feature in the Debug Toolkit is only available for Channel 0. Eye Plot support for Channels other than Channel 0 may be available in a future release of Quartus® Prime.
The P-Tile Avalon® -ST and Avalon® -MM IPs for PCIe support the PCIe Link Inspector in this release. The PCIe Link Inspector allows you to monitor the PCIe link status at the Physical, Data Link and Transaction Layers.
The P-Tile Avalon® -ST IP adds Modelsim support for design example simulation in this release. The P-Tile Avalon® -ST IP can support Modelsim and VCS simulators in the 20.2 release of Quartus® Prime. The P-Tile Avalon® -MM IP still only supports VCS. Other simulators may be supported in a future release.
The independent pin_perst option is no longer available in the P-Tile Avalon® -ST IP in this release. When a x16 port is bifurcated into two x8 ports, a reset via pin_perst impacts both x8 ports.
The P-Tile Avalon® -MM IP for PCIe does not support 10-bit tags for the x16 core in this release. The x16 core of the P-Tile Avalon® -MM IP for PCIe only supports up to 64 outstanding Non-Posted Requests (NPRs) in this release.
The Root Port (RP) BFM for Endpoint configurations is not available in this release. It may be available in a future release. Use a third-party BFM to simulate the P-Tile Root Port design examples.
Configurations with the Adapter enabled are not available in this release. Gen4 x8, 512-bit and Gen4 x4 256-bit configurations are not available in this release.
You cannot change the PCIe SerDes pin allocations for the P-Tile Avalon® -ST and Avalon® -MM IPs for PCIe in the Quartus® Prime project. To ease PCB routing, you can take advantage of the lane reversal and polarity inversion features supported by the P-Tile Avalon® -ST and Avalon® -MM IPs for PCIe.
Table 56.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 S C T H S C T H S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 400 MHz 400 MHz N/A
Gen3 x16 S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 57.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 S C T H S C T H S C T H S C T H N/A N/A 500 MHz 500 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 500 MHz 500 MHz N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 500 MHz 500 MHz N/A
Gen3 x16 S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 58.  P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCIe Support Matrix for Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP EP RP -1 -2 -3
Gen4 x16 S C T H (**) S C T H (*) (**) 350 MHz 350 MHz N/A
Gen4 x8/x8 S C T H N/A S C T H (*) N/A 350 MHz 350 MHz N/A
Gen4 x4/x4/x4/x4 N/A S C T H N/A (**) 350 MHz 350 MHz N/A
Gen3 x16 S C T H (**) S C T H (*) (**) 250 MHz 250 MHz N/A
Gen3 x8/x8 S C T H N/A S C T H (*) N/A 250 MHz 250 MHz N/A
Gen3 x4/x4/x4/x4 N/A S C T H N/A (**) 250 MHz 250 MHz N/A
Note: (*) The design example available in the 20.2 release supports the DMA mode with Data Movers. A design example supporting the Bursting Slave mode may be available in a future release.
Note: (**) This support may be available in a future release of Quartus® Prime.
Table 59.  P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP EP RP -1 -2 -3
Gen4 x16 S C T H (**) S C T H (*) (**) 400 MHz 400 MHz N/A
Gen4 x8/x8 S C T H N/A S C T H (*) N/A 400 MHz 400 MHz N/A
Gen4 x4/x4/x4/x4 N/A S C T H N/A (**) 400 MHz 400 MHz N/A
Gen3 x16 S C T H (**) S C T H (*) (**) 250 MHz 250 MHz N/A
Gen3 x8/x8 S C T H N/A S C T H (*) N/A 250 MHz 250 MHz N/A
Gen3 x4/x4/x4/x4 N/A S C T H N/A (**) 250 MHz 250 MHz N/A
Note: (*) The design example available in the 20.2 release supports the DMA mode with Data Movers. A design example supporting the Bursting Slave mode may be available in a future release.
Note: (**) This support may be available in a future release of Quartus® Prime.
Level Two Title