R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 683501
Date 10/06/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. IP Architecture and Functional Description 3. Parameters 4. Interfaces 5. Advanced Features 6. R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide Archives 7. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide A. Configuration Space Registers B. Root Port Enumeration C. Implementation of Address Translation Services (ATS) in Endpoint Mode D. Packets Forwarded to the User Application in TLP Bypass Mode
1. Introduction x
1.1. Overview 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Performance and Resource Utilization 1.6. IP Core Support Levels
1.1. Overview x
1.1.1. Standards and Specifications Compliance
2. IP Architecture and Functional Description x
2.1. Overview 2.2. PCIe Hard IP Mode 2.3. PIPE Direct Mode
2.2. PCIe Hard IP Mode x
2.2.1. Clocking 2.2.2. Reset 2.2.3. PCI Express Protocol Stack
2.2.3. PCI Express Protocol Stack x
2.2.3.1. PMA/PCS 2.2.3.2. Data Link Layer Overview 2.2.3.3. Transaction Layer Overview
2.3. PIPE Direct Mode x
2.3.1. Clocking 2.3.2. Reset 2.3.3. PIPE Layer
3. Parameters x
3.1. Top-Level Settings 3.2. Core Parameters
4. Interfaces x
4.1. Overview 4.2. Clocks and Resets 4.3. Serial Data Interface 4.4. PCI Express Mode 4.5. PIPE Direct Mode
4.2. Clocks and Resets x
4.2.1. Clocks 4.2.2. Resets
4.4. PCI Express Mode x
4.4.1. Avalon® Streaming Interface 4.4.2. Precision Time Measurement (PTM) Interface 4.4.3. Interrupt Interface 4.4.4. Hard IP Reconfiguration Interface 4.4.5. Error Interface 4.4.6. Completion Timeout Interface 4.4.7. Configuration Intercept Interface 4.4.8. Power Management Interface 4.4.9. Hard IP Status Interface 4.4.10. Page Request Services (PRS) Interface 4.4.11. Function-Level Reset (FLR) Interface 4.4.12. SR-IOV VF Error Flag Interface 4.4.13. General Purpose VSEC Interface
4.4.1. Avalon® Streaming Interface x
4.4.1.1. TLP Header and Data Alignment for the Avalon® streaming RX and TX Interfaces 4.4.1.2. Credit Control 4.4.1.3. Avalon® Streaming RX Interface 4.4.1.4. Avalon® Streaming TX Interface 4.4.1.5. Tag Allocation
4.4.1.2. Credit Control x
4.4.1.2.1. Credit Interface - Data and Header 4.4.1.2.2. Credit Initialization 4.4.1.2.3. Credit Update/Release 4.4.1.2.4. RX Flow Control Interface 4.4.1.2.5. TX Flow Control Interface
4.4.1.2.4. RX Flow Control Interface x
4.4.1.2.4.1. Completion Buffer Size
4.4.1.4. Avalon® Streaming TX Interface x
4.4.1.4.1. Avalon® Streaming TX Interface tx_st_ready_o Behavior
4.4.3. Interrupt Interface x
4.4.3.1. Legacy Interrupts 4.4.3.2. MSI 4.4.3.3. MSI-X
4.4.3.3. MSI-X x
4.4.3.3.1. Implementing MSI-X Interrupts
4.4.8. Power Management Interface x
4.4.8.1. Endpoint D3Hot Entry 4.4.8.2. Endpoint D3Hot Exit
4.5. PIPE Direct Mode x
4.5.1. Data Signals 4.5.2. Message Channel 4.5.3. Deskew Channel 4.5.4. PIPE Direct Reset Sequence 4.5.5. PIPE Direct Speed Change 4.5.6. PIPE Lane Reset Staggering 4.5.7. Unused Lanes in PIPE Direct Mode 4.5.8. PIPE Direct Mode TX/RX Datapaths
4.5.1. Data Signals x
4.5.1.1. Transmit Signals 4.5.1.2. Receive Signals
5. Advanced Features x
5.1. PCIe Port Bifurcation and PHY Channel Mapping 5.2. Virtualization Support 5.3. TLP Bypass Mode
5.2. Virtualization Support x
5.2.1. SR-IOV Support 5.2.2. VirtIO Support
5.2.1. SR-IOV Support x
5.2.1.1. SR-IOV Supported Features List 5.2.1.2. Implementation 5.2.1.3. VF to PF Mapping 5.2.1.4. Function Level Reset (FLR)
5.2.1.2. Implementation x
5.2.1.2.1. VF Error Flag Interface (for x16/x8 Cores Only)
5.2.2. VirtIO Support x
5.2.2.1. VirtIO Supported Features List 5.2.2.2. Overview 5.2.2.3. Parameters 5.2.2.4. VirtIO PCI Configuration Access Interface 5.2.2.5. Registers
5.2.2.5. Registers x
5.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012) 5.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013) 5.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014) 5.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015) 5.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016) 5.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017) 5.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018) 5.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019) 5.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A) 5.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F) 5.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030) 5.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031) 5.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032) 5.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033) 5.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034) 5.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035) 5.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036) 5.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037) 5.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038) 5.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039) 5.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A) 5.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
5.3. TLP Bypass Mode x
5.3.1. Overview 5.3.2. Register Settings for the TLP Bypass Mode 5.3.3. User Avalon Memory-mapped Interface 5.3.4. Avalon® Streaming Interface
5.3.2. Register Settings for the TLP Bypass Mode x
5.3.2.1. TLPBYPASS_ERR_EN (Address 0x1314) 5.3.2.2. TLPBYPASS_ERR_STATUS (Address 0x1310)
5.3.4. Avalon® Streaming Interface x
5.3.4.1. Configuration TLP 5.3.4.2. Transmit Interface 5.3.4.3. Receive Interface 5.3.4.4. Malformed TLP 5.3.4.5. ECRC
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
D. Packets Forwarded to the User Application in TLP Bypass Mode x
D.1. EP TLP Bypass Mode (Upstream) D.2. RC TLP Bypass Mode (Downstream)
1. Introduction
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide Archives
7. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TLP Bypass Mode

4.2.2. Resets

Table 14.  Resets
Name Direction Description EP/RP/BP Asynchronous / Synchronous
pin_perst_n Input

This is the reset signal from the board. This pin is not available to the FPGA user logic. If you want to use the PERST# signal in user logic or in the Intel Signal Tap tool, you need to use the pin_perst_n_o signal.

To prevent potential device degradation, the pin_perst_n signal must not be held active if power is supplied to the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express when the FPGA is in user mode. If the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express is planned to be used but not in the early phases of your design cycle, you must configure it in BTI mode using the following qsf asigment:

set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON

EP/RP/BP Asynchronous
pin_perst_n_o Output This output signal to the FPGA fabric indicates if PERST# is asserted. EP/RP/BP Asynchronous
ninit_done Input

A "1" on this active-low signal indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode.

You need to instantiate the Reset Release IP and connect the output of that IP to ninit_done.

EP/RP/BP Asynchronous
pX_reset_status_n_o Output

This active-low signal is held low until pin_perst_n has been deasserted and the PCIe Hard IP has come out of reset. This signal is synchronous to coreclkout_hip.

When port bifurcation is used, there is one such signal for each Avalon® Streaming interface. Signals for different interfaces are differentiated by the prefixes p<n>.

Traffic between the user logic in the FPGA core and the IP can start when pX_reset_status_n_o is asserted high.

EP/RP/BP Synchronous to coreclkout_hip.
pX_slow_reset_status_n_o Output This is the equivalent signal for pX_reset_status_n_o in the slow_clk domain. EP/RP/BP Synchronous to slow_clk.
LnX_pipe_direct_reset_status_n (X = 0 - 15) Output This active-low per-lane signal is held low until the PHY RX is out of reset, and when deasserted is an indication to the application logic that the RX data transfer is beginning. PIPE mode Synchronous to pipe_direct_pld_tx_clk_out_o.
LnX_pipe_direct_pld_pcs_rst_n_i (X = 0 - 15) Input User logic deasserts this per-lane signal (driving it to "1") as a part of the reset sequence. Follow the reset sequence as shown in PIPE Direct Reset Sequence. PIPE mode Asynchronous

Level Two Title