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1. Introduction
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide Archives
7. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TLP Bypass Mode
4.4.1. Avalon® Streaming Interface
4.4.2. Precision Time Measurement (PTM) Interface
4.4.3. Interrupt Interface
4.4.4. Hard IP Reconfiguration Interface
4.4.5. Error Interface
4.4.6. Completion Timeout Interface
4.4.7. Configuration Intercept Interface
4.4.8. Power Management Interface
4.4.9. Hard IP Status Interface
4.4.10. Page Request Services (PRS) Interface
4.4.11. Function-Level Reset (FLR) Interface
4.4.12. SR-IOV VF Error Flag Interface
4.4.13. General Purpose VSEC Interface
5.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012)
5.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013)
5.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014)
5.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015)
5.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016)
5.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017)
5.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018)
5.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019)
5.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A)
5.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F)
5.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030)
5.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031)
5.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032)
5.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033)
5.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034)
5.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035)
5.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036)
5.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037)
5.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038)
5.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039)
5.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A)
5.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
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3. Parameters
This chapter provides a reference for all the parameters that are configurable in the Intel® Quartus® Prime IP Parameter Editor for the R-tile Avalon® Streaming IP for PCIe.