R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 683501
Date 10/06/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. IP Architecture and Functional Description 3. Parameters 4. Interfaces 5. Advanced Features 6. R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide Archives 7. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide A. Configuration Space Registers B. Root Port Enumeration C. Implementation of Address Translation Services (ATS) in Endpoint Mode D. Packets Forwarded to the User Application in TLP Bypass Mode
1. Introduction x
1.1. Overview 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Performance and Resource Utilization 1.6. IP Core Support Levels
1.1. Overview x
1.1.1. Standards and Specifications Compliance
2. IP Architecture and Functional Description x
2.1. Overview 2.2. PCIe Hard IP Mode 2.3. PIPE Direct Mode
2.2. PCIe Hard IP Mode x
2.2.1. Clocking 2.2.2. Reset 2.2.3. PCI Express Protocol Stack
2.2.3. PCI Express Protocol Stack x
2.2.3.1. PMA/PCS 2.2.3.2. Data Link Layer Overview 2.2.3.3. Transaction Layer Overview
2.3. PIPE Direct Mode x
2.3.1. Clocking 2.3.2. Reset 2.3.3. PIPE Layer
3. Parameters x
3.1. Top-Level Settings 3.2. Core Parameters
4. Interfaces x
4.1. Overview 4.2. Clocks and Resets 4.3. Serial Data Interface 4.4. PCI Express Mode 4.5. PIPE Direct Mode
4.2. Clocks and Resets x
4.2.1. Clocks 4.2.2. Resets
4.4. PCI Express Mode x
4.4.1. Avalon® Streaming Interface 4.4.2. Precision Time Measurement (PTM) Interface 4.4.3. Interrupt Interface 4.4.4. Hard IP Reconfiguration Interface 4.4.5. Error Interface 4.4.6. Completion Timeout Interface 4.4.7. Configuration Intercept Interface 4.4.8. Power Management Interface 4.4.9. Hard IP Status Interface 4.4.10. Page Request Services (PRS) Interface 4.4.11. Function-Level Reset (FLR) Interface 4.4.12. SR-IOV VF Error Flag Interface 4.4.13. General Purpose VSEC Interface
4.4.1. Avalon® Streaming Interface x
4.4.1.1. TLP Header and Data Alignment for the Avalon® streaming RX and TX Interfaces 4.4.1.2. Credit Control 4.4.1.3. Avalon® Streaming RX Interface 4.4.1.4. Avalon® Streaming TX Interface 4.4.1.5. Tag Allocation
4.4.1.2. Credit Control x
4.4.1.2.1. Credit Interface - Data and Header 4.4.1.2.2. Credit Initialization 4.4.1.2.3. Credit Update/Release 4.4.1.2.4. RX Flow Control Interface 4.4.1.2.5. TX Flow Control Interface
4.4.1.2.4. RX Flow Control Interface x
4.4.1.2.4.1. Completion Buffer Size
4.4.1.4. Avalon® Streaming TX Interface x
4.4.1.4.1. Avalon® Streaming TX Interface tx_st_ready_o Behavior
4.4.3. Interrupt Interface x
4.4.3.1. Legacy Interrupts 4.4.3.2. MSI 4.4.3.3. MSI-X
4.4.3.3. MSI-X x
4.4.3.3.1. Implementing MSI-X Interrupts
4.4.8. Power Management Interface x
4.4.8.1. Endpoint D3Hot Entry 4.4.8.2. Endpoint D3Hot Exit
4.5. PIPE Direct Mode x
4.5.1. Data Signals 4.5.2. Message Channel 4.5.3. Deskew Channel 4.5.4. PIPE Direct Reset Sequence 4.5.5. PIPE Direct Speed Change 4.5.6. PIPE Lane Reset Staggering 4.5.7. Unused Lanes in PIPE Direct Mode 4.5.8. PIPE Direct Mode TX/RX Datapaths
4.5.1. Data Signals x
4.5.1.1. Transmit Signals 4.5.1.2. Receive Signals
5. Advanced Features x
5.1. PCIe Port Bifurcation and PHY Channel Mapping 5.2. Virtualization Support 5.3. TLP Bypass Mode
5.2. Virtualization Support x
5.2.1. SR-IOV Support 5.2.2. VirtIO Support
5.2.1. SR-IOV Support x
5.2.1.1. SR-IOV Supported Features List 5.2.1.2. Implementation 5.2.1.3. VF to PF Mapping 5.2.1.4. Function Level Reset (FLR)
5.2.1.2. Implementation x
5.2.1.2.1. VF Error Flag Interface (for x16/x8 Cores Only)
5.2.2. VirtIO Support x
5.2.2.1. VirtIO Supported Features List 5.2.2.2. Overview 5.2.2.3. Parameters 5.2.2.4. VirtIO PCI Configuration Access Interface 5.2.2.5. Registers
5.2.2.5. Registers x
5.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012) 5.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013) 5.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014) 5.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015) 5.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016) 5.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017) 5.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018) 5.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019) 5.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A) 5.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F) 5.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030) 5.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031) 5.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032) 5.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033) 5.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034) 5.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035) 5.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036) 5.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037) 5.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038) 5.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039) 5.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A) 5.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
5.3. TLP Bypass Mode x
5.3.1. Overview 5.3.2. Register Settings for the TLP Bypass Mode 5.3.3. User Avalon Memory-mapped Interface 5.3.4. Avalon® Streaming Interface
5.3.2. Register Settings for the TLP Bypass Mode x
5.3.2.1. TLPBYPASS_ERR_EN (Address 0x1314) 5.3.2.2. TLPBYPASS_ERR_STATUS (Address 0x1310)
5.3.4. Avalon® Streaming Interface x
5.3.4.1. Configuration TLP 5.3.4.2. Transmit Interface 5.3.4.3. Receive Interface 5.3.4.4. Malformed TLP 5.3.4.5. ECRC
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
D. Packets Forwarded to the User Application in TLP Bypass Mode x
D.1. EP TLP Bypass Mode (Upstream) D.2. RC TLP Bypass Mode (Downstream)
1. Introduction
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide Archives
7. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TLP Bypass Mode

5.2.2.5. Registers

The following VirtIO capability structure registers references apply to each PF and VF. Addresses shown are register addresses.

Table 54.  PF/VF Capability Link List
Capability Start Byte Address Last Byte Address DW Count
Type0 0x00 0x3F 16
PM (PF only) 0x40 0x47 2
Reserved 0x48 0x4F 2
VirtIO Common Configuration 0x50 0x5F 4
VirtIO ISR Configuration 0x60 0x6F 4
PCIe 0x70 0xAB 15
Reserved 0xAC 0xAF 1
MSIX 0xB0 0xBB 3
Reserved 0xBC 0xBF 1
VirtIO Notify Configuration 0xC0 0xD3 5
VirtIO Device-Specific Configuration 0xD4 0xE3 4
VirtIO PCI Configuration Access 0xE4 0xF7 5
Reserved 0xF8 0xFF 2
Table 55.  VirtIO Common Configuration Capability Structure
Address Name Description
014 Common Configuration Capability Register Capability ID, next capability pointer, capability length
015 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
016 BAR Offset Register Indicates starting address of the structure within the BAR
017 Structure Length Register Indicates length of structure
VirtIO Notifications Capability Structure
030 Notifications Capability Register Capability ID, next capability pointer, capability length
031 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
032 BAR Offset Register Indicates starting address of the structure within the BAR
033 Structure Length Register Indicates length of structure
034 Notify Off Multiplier Multiplier for queue_notify_off
VirtIO ISR Status Capability Structure
018 ISR Status Capability Register Capability ID, next capability pointer, capability length
019 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
020 BAR Offset Register Indicates starting address of the structure within the BAR
021 Structure Length Register Indicates length of structure
VirtIO Device-Specific Capability Structure (Optional)
035 Device Specific Capability Register Capability ID, next capability pointer, capability length
036 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
037 BAR Offset Register Indicates starting address of the structure within the BAR
038 Structure Length Register Indicates length of structure
VirtIO PCI Configuration Access Structure
039 PCI Configuration Access Capability Register Capability ID, next capability pointer, capability length
040 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
041 BAR Offset Register Indicates starting address of the structure within the BAR
042 Structure Length Register Indicates length of structure
043 PCI Configuration Data Data for BAR access
Level Two Title