Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

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ID 683486
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP 2. Low Latency E-Tile 40G Ethernet IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives 11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core 12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP x
1.1. Release Information 1.2. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Supported Features 1.3. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.4. Resource Utilization
1.3. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Low Latency E-Tile 40G Ethernet IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Ethernet Adaptation Flow 3.5.3. Placement Settings for the Low Latency E-Tile 40G Ethernet Core
3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency E-Tile 40G Ethernet Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Low Latency E-Tile 40G Ethernet Core Functional Description x
4.1.1. Low Latency E-Tile 40G Ethernet Core TX MAC Datapath 4.1.2. Low Latency E-Tile 40G Ethernet Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Flow Control
4.1.1. Low Latency E-Tile 40G Ethernet Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC-32) Insertion
4.1.2. Low Latency E-Tile 40G Ethernet Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.1.4. Flow Control x
4.1.4.1. TX Pause/PFC Flow Control Transmission 4.1.4.2. XON/XOFF Pause Frames
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers Signals 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP
2. Low Latency E-Tile 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives
11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core
12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

6.5. Avalon® Memory-Mapped Management Interface

You access control and status registers using an Avalon® memory-mapped management interface. The interface responds regardless of the link status. It also responds when the IP core is in a reset state driven by any reset signal or soft reset other than the csr_rst_n signal. Asserting the csr_rst_n signal resets all statistics registers; while this reset is in process, the Avalon® memory-mapped management interface does not respond.
Table 17.   Avalon® Memory-Mapped Management Interface
Note: All status_* signals are synchronous to clk_status signal.

Signal

Direction

Description

clk_status Input The clock that drives the control and status registers. The frequency of this clock is 100-161 MHz.
status_addr[15:0] Input

Drives the Avalon® memory-mapped register address.

status_read Input

When asserted, specifies a read request.

status_write Input When asserted, specifies a write request.
status_readdata[31:0] Output Drives read data. Valid when status_readdata_valid is asserted.
status_readdata_valid Output When asserted, indicates that status_read_data[31:0] is valid.
status_writedata[31:0] Input Drives the write data. The packet can end at any byte position. The empty bytes are the low-order bytes.
status_waitrequest Output Indicates that the control and status interface is not ready to complete the transaction. status_waitrequest is only used for read transactions.
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