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Answers to Top FAQs
1. Introduction to Quartus® Prime Pro Edition
2. Quick Start Steps
3. Planning FPGA Design for RTL Flow
4. Working With Intel® FPGA IP Cores
5. Creating a New FPGA Design Project
6. Migrate Your FPGA Design Project
7. Managing Quartus® Prime Projects
8. Next Steps After Getting Started
A. Using the Design Space Explorer II
B. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started
4.1. IP Catalog and Parameter Editor
4.2. Installing and Licensing Intel® FPGA IP Cores
4.3. IP General Settings
4.4. Adding IP to IP Catalog
4.5. Best Practices for Intel® FPGA IP
4.6. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
4.7. IP Core Generation Output ( Quartus® Prime Pro Edition)
4.8. Scripting IP Core Generation
4.9. Modifying an IP Variation
4.10. Upgrading IP Cores
4.11. Simulating Intel® FPGA IP Cores
4.12. Generating Simulation Files for Platform Designer Systems and IP Variants
4.13. Synthesizing IP Cores in Other EDA Tools
4.14. Instantiating IP Cores in HDL
4.15. Support for the IEEE 1735 Encryption Standard
4.16. Related Trainings and Resources
6.1.2.1. Modifying Entity Name Assignments
6.1.2.2. Resolving Timing Constraint Entity Names
6.1.2.3. Verifying Generated Node Name Assignments
6.1.2.4. Replace Logic Lock (Standard) Regions
6.1.2.5. Modifying Signal Tap Logic Analyzer Files
6.1.2.6. Removing References to .qip Files
6.1.2.7. Removing Unsupported Feature Assignments
6.1.4.1. Verifying Verilog Compilation Unit
6.1.4.2. Updating Entity Auto-Discovery
6.1.4.3. Ensuring Distinct VHDL Namespace for Each Library
6.1.4.4. Removing Unsupported Parameter Passing
6.1.4.5. Removing Unsized Constant from WYSIWYG Instantiation
6.1.4.6. Removing Non-Standard Pragmas
6.1.4.7. Declaring Objects Before Initial Values
6.1.4.8. Confining SystemVerilog Features to SystemVerilog Files
6.1.4.9. Avoiding Assignment Mixing in Always Blocks
6.1.4.10. Avoiding Unconnected, Non-Existent Ports
6.1.4.11. Avoiding Invalid Parameter Ranges
6.1.4.12. Updating Verilog HDL and VHDL Type Mapping
6.1.4.13. Converting Symbolic BDF Files to Acceptable File Formats
7.1. Viewing Basic Project Information
7.2. Managing Project Settings
7.3. Viewing Parameter Settings From the Project Navigator
7.4. Managing Logic Design Files
7.5. Managing Timing Constraints
7.6. Integrating Other EDA Tools
7.7. Exporting Compilation Results
7.8. Archiving Projects
7.9. Command-Line Interface
7.10. Related Trainings
7.7.1. Exporting a Version-Compatible Compilation Database
7.7.2. Importing a Version-Compatible Compilation Database
7.7.3. Creating a Design Partition
7.7.4. Exporting a Design Partition
7.7.5. Reusing a Design Partition
7.7.6. Viewing Quartus Database File Information
7.7.7. Clearing Compilation Results
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A.3. Setting Up Remote Farm Using Design Space Explorer II
To launch Design Space Explorer II, in the Quartus® Prime Pro Edition GUI, click Tools > Launch Design Space Explorer II. Click Yes to the message that appears. This closes the Quartus® Prime software and launches the Design Space Explorer II.
Under the Project tab, click Open Project to add your project to the Design Space Explorer II. Refer to Project Page (Design Space Explorer II) for information about all options on this tab.
Use one of the following methods to set up your remote farm:
LSF Remote Farm
Follow these steps to set up your remote machine using the Design Space Explorer II and LSF remote compilation type:
- Ensure you have set up your LSF environment. If not, request your IT administrator to set up the LSF environment.
- Once the LSF environment is ready, launch the command line interface and execute the bsub sleep 60 command.
- Under the Setup tab, select Remote compilation type and choose the LSF option from the drop-down list. Populate all mandatory settings under Specify custom settings for LSF with the LSF environment-specific information.
Refer to Setup Page (Design Space Explorer II) for information about all options on this tab.
- Customize the settings as necessary.
- Under the Exploration tab, expand the Exploration Points section.
- Select Design exploration.
- Under Exploration Options, select Seed Sweep Only.
- Under Seeds, select Create. By default, it must be set to 2 seeds.
- Click Start. Wait until the design exploration is complete.
- Click the Results tab to review the status of the design exploration.
SSH Remote Farm
Follow these steps to set up your remote machine using the Design Space Explorer II and SSH remote compilation type:
- Install the open-source PuTTY Key Generator tool and launch it.
- Click Generate to generate the public/private key pair.
- Enter the key passphrase.
- Click Save private key to save the private key with a .ppk extension.
- Click Save public key to save the public key as putty_gen_public_key.pub.
- On your machine, change to the SSH directory and copy the contents of the putty_gen_public_key.pub file.
- In the Design Space, under the Setup tab, select SSH compilation type and specify the following:
- For Hostname, enter the server name.
- For private_key, enter the path to your private key (.ppk file).
- For SSH Client, enter the path to the plink.exe file. You can find this in the same directory where you installed the PuTTy tool.
- For Farm Operating System, enter your system type (linux or windows).
The remaining settings are similar to LSF settings. Refer to Setup Page (Design Space Explorer II) for information about all options on this tab.
- Under the Exploration tab, expand the Exploration Points section.
- Select Design exploration.
- Under Exploration Options, select Seed Sweep Only.
- Under Seeds, select Create. By default, it must be set to 2 seeds.
- Click Start. Wait until the design exploration is complete.
- Click the Results tab to review the status of the design exploration.