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Answers to Top FAQs
1. Introduction to Quartus® Prime Pro Edition
2. Quick Start Steps
3. Planning FPGA Design for RTL Flow
4. Working With Intel® FPGA IP Cores
5. Creating a New FPGA Design Project
6. Migrate Your FPGA Design Project
7. Managing Quartus® Prime Projects
8. Next Steps After Getting Started
A. Using the Design Space Explorer II
B. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started
4.1. IP Catalog and Parameter Editor
4.2. Installing and Licensing Intel® FPGA IP Cores
4.3. IP General Settings
4.4. Adding IP to IP Catalog
4.5. Best Practices for Intel® FPGA IP
4.6. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
4.7. IP Core Generation Output ( Quartus® Prime Pro Edition)
4.8. Scripting IP Core Generation
4.9. Modifying an IP Variation
4.10. Upgrading IP Cores
4.11. Simulating Intel® FPGA IP Cores
4.12. Generating Simulation Files for Platform Designer Systems and IP Variants
4.13. Synthesizing IP Cores in Other EDA Tools
4.14. Instantiating IP Cores in HDL
4.15. Support for the IEEE 1735 Encryption Standard
4.16. Related Trainings and Resources
6.1.2.1. Modifying Entity Name Assignments
6.1.2.2. Resolving Timing Constraint Entity Names
6.1.2.3. Verifying Generated Node Name Assignments
6.1.2.4. Replace Logic Lock (Standard) Regions
6.1.2.5. Modifying Signal Tap Logic Analyzer Files
6.1.2.6. Removing References to .qip Files
6.1.2.7. Removing Unsupported Feature Assignments
6.1.4.1. Verifying Verilog Compilation Unit
6.1.4.2. Updating Entity Auto-Discovery
6.1.4.3. Ensuring Distinct VHDL Namespace for Each Library
6.1.4.4. Removing Unsupported Parameter Passing
6.1.4.5. Removing Unsized Constant from WYSIWYG Instantiation
6.1.4.6. Removing Non-Standard Pragmas
6.1.4.7. Declaring Objects Before Initial Values
6.1.4.8. Confining SystemVerilog Features to SystemVerilog Files
6.1.4.9. Avoiding Assignment Mixing in Always Blocks
6.1.4.10. Avoiding Unconnected, Non-Existent Ports
6.1.4.11. Avoiding Invalid Parameter Ranges
6.1.4.12. Updating Verilog HDL and VHDL Type Mapping
6.1.4.13. Converting Symbolic BDF Files to Acceptable File Formats
7.1. Viewing Basic Project Information
7.2. Managing Project Settings
7.3. Viewing Parameter Settings From the Project Navigator
7.4. Managing Logic Design Files
7.5. Managing Timing Constraints
7.6. Integrating Other EDA Tools
7.7. Exporting Compilation Results
7.8. Archiving Projects
7.9. Command-Line Interface
7.10. Related Trainings
7.7.1. Exporting a Version-Compatible Compilation Database
7.7.2. Importing a Version-Compatible Compilation Database
7.7.3. Creating a Design Partition
7.7.4. Exporting a Design Partition
7.7.5. Reusing a Design Partition
7.7.6. Viewing Quartus Database File Information
7.7.7. Clearing Compilation Results
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6.1.2.5. Modifying Signal Tap Logic Analyzer Files
Quartus® Prime Pro Edition introduces new methodology for entity names, settings, and assignments. These changes impact the processing of Signal Tap Logic Analyzer Files (.stp).
If you migrate a project that includes .stp files generated by other Quartus software products, you must make the following changes to migrate to the Quartus® Prime Pro Edition:
- Remove entity names from .stp files. The Signal Tap Logic Analyzer allows without error, but ignores, entity names in .stp files. Remove entity names from .stp files for migration to Quartus® Prime Pro Edition:
- Click View > Node Finder to locate and remove appropriate nodes. Use Node Finder options to filter on nodes.
- Click Processing > Start > Start Analysis & Elaboration to repopulate the database and add valid node names.
- Remove post-fit nodes. Quartus® Prime Pro Edition uses a different post-fit node naming scheme than other Quartus software products.
- Remove post-fit tap node names originating from other Quartus software products.
- Click View > Node Finder to locate and remove post-fit nodes. Use Node Finder options to filter on nodes.
- Click Processing > Start Compilation to repopulate the database and add valid post-fit nodes.
- Run an initial compilation in Quartus® Prime Pro Edition from the GUI. The Compiler automatically removes Signal Tap assignments originating other Quartus software products. Alternatively, from the command-line, run quartus_stp once on the project to remove outmoded assignments.
Note: quartus_stp introduces no migration impact in the Quartus® Prime Pro Edition. Your scripts require no changes to quartus_stp for migration.
- Modify .sdc constraints for JTAG. Quartus® Prime Pro Edition does not support embedded .sdc constraints for JTAG signals. Modify the timing template to suit the design's JTAG driver and board.