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Answers to Top FAQs
1. Introduction to Quartus® Prime Pro Edition
2. Quick Start Steps
3. Planning FPGA Design for RTL Flow
4. Working With Intel® FPGA IP Cores
5. Creating a New FPGA Design Project
6. Migrate Your FPGA Design Project
7. Managing Quartus® Prime Projects
8. Next Steps After Getting Started
A. Using the Design Space Explorer II
B. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started
4.1. IP Catalog and Parameter Editor
4.2. Installing and Licensing Intel® FPGA IP Cores
4.3. IP General Settings
4.4. Adding IP to IP Catalog
4.5. Best Practices for Intel® FPGA IP
4.6. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
4.7. IP Core Generation Output ( Quartus® Prime Pro Edition)
4.8. Scripting IP Core Generation
4.9. Modifying an IP Variation
4.10. Upgrading IP Cores
4.11. Simulating Intel® FPGA IP Cores
4.12. Generating Simulation Files for Platform Designer Systems and IP Variants
4.13. Synthesizing IP Cores in Other EDA Tools
4.14. Instantiating IP Cores in HDL
4.15. Support for the IEEE 1735 Encryption Standard
4.16. Related Trainings and Resources
6.1.2.1. Modifying Entity Name Assignments
6.1.2.2. Resolving Timing Constraint Entity Names
6.1.2.3. Verifying Generated Node Name Assignments
6.1.2.4. Replace Logic Lock (Standard) Regions
6.1.2.5. Modifying Signal Tap Logic Analyzer Files
6.1.2.6. Removing References to .qip Files
6.1.2.7. Removing Unsupported Feature Assignments
6.1.4.1. Verifying Verilog Compilation Unit
6.1.4.2. Updating Entity Auto-Discovery
6.1.4.3. Ensuring Distinct VHDL Namespace for Each Library
6.1.4.4. Removing Unsupported Parameter Passing
6.1.4.5. Removing Unsized Constant from WYSIWYG Instantiation
6.1.4.6. Removing Non-Standard Pragmas
6.1.4.7. Declaring Objects Before Initial Values
6.1.4.8. Confining SystemVerilog Features to SystemVerilog Files
6.1.4.9. Avoiding Assignment Mixing in Always Blocks
6.1.4.10. Avoiding Unconnected, Non-Existent Ports
6.1.4.11. Avoiding Invalid Parameter Ranges
6.1.4.12. Updating Verilog HDL and VHDL Type Mapping
6.1.4.13. Converting Symbolic BDF Files to Acceptable File Formats
7.1. Viewing Basic Project Information
7.2. Managing Project Settings
7.3. Viewing Parameter Settings From the Project Navigator
7.4. Managing Logic Design Files
7.5. Managing Timing Constraints
7.6. Integrating Other EDA Tools
7.7. Exporting Compilation Results
7.8. Archiving Projects
7.9. Command-Line Interface
7.10. Related Trainings
7.7.1. Exporting a Version-Compatible Compilation Database
7.7.2. Importing a Version-Compatible Compilation Database
7.7.3. Creating a Design Partition
7.7.4. Exporting a Design Partition
7.7.5. Reusing a Design Partition
7.7.6. Viewing Quartus Database File Information
7.7.7. Clearing Compilation Results
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4.11.2.1. Generating a Combined Simulator Setup Script
You can run the Generate Simulator Setup Script for IP command to generate a combined simulator setup script.
You can then source this combined script from a top-level simulation script. Click Tools > Generate Simulator Setup Script for IP (or use of the ip-setup-simulation utility at the command-line) to generate or update the combined scripts, after any of the following occur:
- IP core initial generation or regeneration with new parameters
- Quartus® Prime software version upgrade
- IP core version upgrade
Utility | Syntax |
---|---|
ip-setup-simulation generates a combined, version-independent simulation script for all Intel® FPGA IP cores in your project. The command also automates regeneration of the script after upgrading software or IP versions. Use the compile-to-work option to compile all simulation files into a single work library if your simulation environment requires. Use the --use-relative-paths option to use relative paths whenever possible. | ip-setup-simulation --quartus-project=<my proj> --output-directory=<my_dir> --use-relative-paths --compile-to-work --use-relative-paths and --compile-to-work are optional. For command-line help listing all options for these executables, type: <utility name> --help. |
To generate a combined simulator setup script for all project IP cores for each simulator:3
- Click Tools > Generate Simulator Setup Script for IP (or run the ip-setup-simulation utility). Specify the Output Directory and library compilation options. Click OK to generate the file. By default, the files generate into the /<project directory>/<simulator>/ directory using relative paths.
Note: For designs with F-tile IP, do not turn on the Use top-level entity names from Quartus project option.Figure 25. Generate Simulator Setup Script for IP Dialog Box
- To incorporate the generated simulator setup script into your top-level simulation script, refer to the template section in the generated simulator setup script as a guide to creating a top-level script:
- Copy the specified template sections from the simulator-specific generated scripts and paste them into a new top-level file.
- Remove the comments at the beginning of each line from the copied template sections.
- Specify the customizations you require to match your design simulation requirements, for example:
- Specify the TOP_LEVEL_NAME variable to the design’s simulation top-level file. The top-level entity of your simulation is often a testbench that instantiates your design. Then, your design instantiates IP cores or Platform Designer systems. Set the value of TOP_LEVEL_NAME to the top-level entity.
- If necessary, set the QSYS_SIMDIR variable to point to the location of the generated IP simulation files.
- Specify any other changes, such as using the grep command-line utility to search a transcript file for error signatures, or e-mail a report.
- Re-run Tools > Generate Simulator Setup Script for IP (or ip-setup-simulation) after regeneration of an IP variation.
Related Information
3 If your design contains one or more F-tile IPs, you must first perform Start Analysis & Elaboration and then Support-Logic Generation before performing these steps.