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Answers to Top FAQs
1. Introduction to Quartus® Prime Pro Edition
2. Quick Start Steps
3. Planning FPGA Design for RTL Flow
4. Working With Intel® FPGA IP Cores
5. Creating a New FPGA Design Project
6. Migrate Your FPGA Design Project
7. Managing Quartus® Prime Projects
8. Next Steps After Getting Started
A. Using the Design Space Explorer II
B. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started
4.1. IP Catalog and Parameter Editor
4.2. Installing and Licensing Intel® FPGA IP Cores
4.3. IP General Settings
4.4. Adding IP to IP Catalog
4.5. Best Practices for Intel® FPGA IP
4.6. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
4.7. IP Core Generation Output ( Quartus® Prime Pro Edition)
4.8. Scripting IP Core Generation
4.9. Modifying an IP Variation
4.10. Upgrading IP Cores
4.11. Simulating Intel® FPGA IP Cores
4.12. Generating Simulation Files for Platform Designer Systems and IP Variants
4.13. Synthesizing IP Cores in Other EDA Tools
4.14. Instantiating IP Cores in HDL
4.15. Support for the IEEE 1735 Encryption Standard
4.16. Related Trainings and Resources
6.1.2.1. Modifying Entity Name Assignments
6.1.2.2. Resolving Timing Constraint Entity Names
6.1.2.3. Verifying Generated Node Name Assignments
6.1.2.4. Replace Logic Lock (Standard) Regions
6.1.2.5. Modifying Signal Tap Logic Analyzer Files
6.1.2.6. Removing References to .qip Files
6.1.2.7. Removing Unsupported Feature Assignments
6.1.4.1. Verifying Verilog Compilation Unit
6.1.4.2. Updating Entity Auto-Discovery
6.1.4.3. Ensuring Distinct VHDL Namespace for Each Library
6.1.4.4. Removing Unsupported Parameter Passing
6.1.4.5. Removing Unsized Constant from WYSIWYG Instantiation
6.1.4.6. Removing Non-Standard Pragmas
6.1.4.7. Declaring Objects Before Initial Values
6.1.4.8. Confining SystemVerilog Features to SystemVerilog Files
6.1.4.9. Avoiding Assignment Mixing in Always Blocks
6.1.4.10. Avoiding Unconnected, Non-Existent Ports
6.1.4.11. Avoiding Invalid Parameter Ranges
6.1.4.12. Updating Verilog HDL and VHDL Type Mapping
6.1.4.13. Converting Symbolic BDF Files to Acceptable File Formats
7.1. Viewing Basic Project Information
7.2. Managing Project Settings
7.3. Viewing Parameter Settings From the Project Navigator
7.4. Managing Logic Design Files
7.5. Managing Timing Constraints
7.6. Integrating Other EDA Tools
7.7. Exporting Compilation Results
7.8. Archiving Projects
7.9. Command-Line Interface
7.10. Related Trainings
7.7.1. Exporting a Version-Compatible Compilation Database
7.7.2. Importing a Version-Compatible Compilation Database
7.7.3. Creating a Design Partition
7.7.4. Exporting a Design Partition
7.7.5. Reusing a Design Partition
7.7.6. Viewing Quartus Database File Information
7.7.7. Clearing Compilation Results
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8.1. Additional Resources
Resource | Description |
---|---|
Intel® Community for FPGA Intellectual Property | Allows you to post queries and get responses to Intel® FPGA IP-related issues. |
Intel® Community for Quartus® Prime Software | Allows you to post queries and get responses to Quartus® Prime software-related issues. |
Intel® Community for Intel® FPGA Software Installation and Licensing | Allows you to post queries and get responses to Intel® FPGA software installation and licensing issues. |
Intel® FPGA Knowledge Base | Provides links to applicable articles that span a variety of Quartus® Prime software-related issues. |
Intel® FPGA Self-Service Licensing Center | Provides support for licensing Intel® FPGA software. |
Quartus® Prime Pro Edition User Guide: Design Recommendations | Describes best practices for designing FPGAs with the Quartus® Prime Pro Edition software. |
Quartus® Prime Pro Edition User Guide: Design Compilation | Describes how to set up, run, and optimize for all stages of the Quartus® Prime Pro Edition software compiler. The compiler synthesizes, places, and routes your design before generating a device programming file. |
Quartus® Prime Pro Edition User Guide: Scripting | Describes use of Tcl and command line scripts to control the Quartus® Prime Pro Edition software and to perform a wide range of functions, such as managing projects, specifying constraints, running compilation or timing analysis, or generating reports. |
Scripting with Quartus® Prime Software | Demonstrates how to use the command-line executables for the Quartus® Prime design flow. |
Quartus® Prime Pro Edition User Guide: Third-party Simulation | Describes RTL- and gate-level design simulation support for third-party simulation tools by Aldec*, Cadence*, Mentor Graphics*, and Synopsys* that allow you to verify design behavior before device programming. Includes simulator support, simulation flows, and simulating Intel® FPGA IP. |
Questa*-Intel® FPGA Edition Quick-Start: Quartus® Prime Pro Edition User Guide | Demonstrates how to simulate a Quartus® Prime Pro Edition design in the Questa*-Intel® FPGA Edition simulator. |
How to Setup RTL Simulations in Quartus® Prime, Platform Designer, and Third-Party Simulators | Describes how to setup an RTL-based simulation using the IP setup simulation utility. |
Quartus® Prime Pro Edition Software User Guides Collection | Each user guide in the collection covers a specific topic and is designed to help you easily and efficiently find the information you need to see your design through to completion. |