Intel® FPGA Power and Thermal Calculator User Guide

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ID 683445
Date 9/26/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Overview of the Intel® FPGA Power and Thermal Calculator 2. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator 3. Intel® FPGA Power and Thermal Calculator Graphical User Interface 4. Intel® FPGA Power and Thermal Calculator Pages 5. Factors Affecting the Accuracy of the Intel® FPGA PTC 6. Intel® FPGA Power and Thermal Calculator User Guide Archive 7. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide A. Measuring Static Power
1. Overview of the Intel® FPGA Power and Thermal Calculator x
1.1. Accessing the Intel FPGA Power and Thermal Calculators 1.2. Intel® FPGA PTC Power Model Status 1.3. Definitions of Power Terms Used in this Document
2. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator x
2.1. Estimating Power Before Starting the FPGA Design 2.2. Estimating Power While Creating the FPGA Design 2.3. Estimating Power After Completing the FPGA Design 2.4. Estimating Power for Dual-Core Devices
2.2. Estimating Power While Creating the FPGA Design x
2.2.1. Importing a .qptc File Generated in the Quartus® Prime Power Analyzer
3. Intel® FPGA Power and Thermal Calculator Graphical User Interface x
3.1. Intel® FPGA PTC Select Family Dialog Box 3.2. Intel® FPGA PTC Primary GUI Components 3.3. Intel® FPGA PTC - IP Wizard 3.4. Intel® FPGA PTC Searchable Drop-Down Lists 3.5. Deleting Rows from Data Entry Pages 3.6. Finding Resources Using the Find Dialog Box
3.2. Intel® FPGA PTC Primary GUI Components x
3.2.1. Intel® FPGA PTC Data Entry Pages 3.2.2. Intel® FPGA PTC Design Hierarchy 3.2.3. Intel® FPGA PTC IP Power Summary 3.2.4. Intel® FPGA PTC Field Types 3.2.5. Intel® FPGA PTC Data Entry Error Messages
3.2.2. Intel® FPGA PTC Design Hierarchy x
3.2.2.1. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator 3.2.2.2. Entering Hierarchy Information Into the Intel® FPGA PTC 3.2.2.3. Exporting, Importing, Duplicating, Renaming, and Deleting Hierarchies in the Intel® FPGA PTC 3.2.2.4. Bulk Editing Hierarchies in the Intel FPGA PTC
3.2.4. Intel® FPGA PTC Field Types x
3.2.4.1. Intel® FPGA PTC Input Field Dependencies
4. Intel® FPGA Power and Thermal Calculator Pages x
4.1. Intel® FPGA PTC - Power Summary/Navigation 4.2. Intel® FPGA PTC - Common Page Elements 4.3. Intel® FPGA PTC - Main Page 4.4. Intel® FPGA PTC - Logic Page 4.5. Intel® FPGA PTC - RAM Page 4.6. Intel® FPGA PTC - DSP Page 4.7. Intel® FPGA PTC - Clock Page 4.8. Intel® FPGA PTC - PLL Page 4.9. Intel® FPGA PTC - I/O Page 4.10. Intel® FPGA PTC - Transceiver Page 4.11. Intel® FPGA PTC - HPS Page 4.12. Intel® FPGA PTC - Crypto Page 4.13. Intel FPGA PTC - NOC Page 4.14. Intel® FPGA PTC - HBM Page 4.15. Intel® FPGA PTC - Thermal Page 4.16. Intel® FPGA PTC - Report Page
4.3. Intel® FPGA PTC - Main Page x
4.3.1. Intel® FPGA PTC - Device Selection and Thermal Analysis Windows
4.10. Intel® FPGA PTC - Transceiver Page x
4.10.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
5. Factors Affecting the Accuracy of the Intel® FPGA PTC x
5.1. Toggle Rate 5.2. I/O Bank Allocation
Answers to Top FAQs
1. Overview of the Intel® FPGA Power and Thermal Calculator
2. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator
3. Intel® FPGA Power and Thermal Calculator Graphical User Interface
4. Intel® FPGA Power and Thermal Calculator Pages
5. Factors Affecting the Accuracy of the Intel® FPGA PTC
6. Intel® FPGA Power and Thermal Calculator User Guide Archive
7. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide
A. Measuring Static Power

3.2.1. Intel® FPGA PTC Data Entry Pages

On the data entry pages you enter information about your design that informs the power estimation calculations. The Intel® FPGA Power and Thermal Calculator (PTC) uses the values that you specify on the data entry pages to calculate the power consumption and other data.

There are differences in the data entry page contents, depending on whether you are targeting an Agilex™ FPGA portfolio device or an Stratix® 10 device.

The following data entry pages are available in the Intel® FPGA PTC:

Table 6.  PTC Data Entry Pages
PTC Data Page Description
Main Allows you to specify device, package, and cooling information, and displays thermal analysis information pertaining to constant junction temperatures.
Logic Allows you to specify the properties of logic resources for all entities in your design.
RAM Allows you to specify the properties of design entities implemented in RAM blocks. Specify the RAM type, data width, RAM depth (if applicable), RAM mode, and port parameters for these entities in your design.
DSP Allows you to specify the properties of DSP design entities. Specify the DSP configuration, clock frequency, toggle percentage, and register usage for the DSPs in your design.
Clock Allows you to specify the properties of the clock networks of separate clock domains in your design. Specify the clock domain name, clock frequency, total fan-out, and other properties about the clocks in your design.
PLL Allows you to specify the properties of one or more PLLs in your design.
I/O Allows you to specify the properties of design entities using general-purpose I/O pins. This page does not apply to transceiver I/O pins. Specify I/O standard, input termination, current strength or output termination, data rate, clock frequency, output enable static probability, and capacitive load for the I/O in your design.
Transceiver Allows you to specify the transceiver resources and their settings for your design entities.
HPS Allows you to specify the properties of entities that include a hard processor system (HPS). Specify the HPS entity and full hierarchy name, the voltage, CPU frequency, CPU application, and number of CPU cores.
Crypto Allows you to specify the properties of crypto resources and their settings for all entities in your design, such as the entity name, full hierarchy name, and number of instances. ( Agilex™ FPGA portfolio devices with crypto blocks only).
NOC The dynamic power consumed by the network-on-chip system (NoC). ( Agilex™ 7 M-Series devices only.)
HBM Allows you to specify the properties of high-bandwidth memory (HBM) entities in your design. ( Stratix® 10 devices with HBM blocks only)
Thermal Allows you to specify the temperature requirements for your design and displays thermal power and thermal analysis information.
Report Reports the per-rail currents that the Intel® FPGA Power and Thermal Calculator (PTC) calculates.
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