Intel® FPGA Power and Thermal Calculator User Guide

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ID 683445
Date 9/26/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Overview of the Intel® FPGA Power and Thermal Calculator 2. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator 3. Intel® FPGA Power and Thermal Calculator Graphical User Interface 4. Intel® FPGA Power and Thermal Calculator Pages 5. Factors Affecting the Accuracy of the Intel® FPGA PTC 6. Intel® FPGA Power and Thermal Calculator User Guide Archive 7. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide A. Measuring Static Power
1. Overview of the Intel® FPGA Power and Thermal Calculator x
1.1. Accessing the Intel FPGA Power and Thermal Calculators 1.2. Intel® FPGA PTC Power Model Status 1.3. Definitions of Power Terms Used in this Document
2. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator x
2.1. Estimating Power Before Starting the FPGA Design 2.2. Estimating Power While Creating the FPGA Design 2.3. Estimating Power After Completing the FPGA Design 2.4. Estimating Power for Dual-Core Devices
2.2. Estimating Power While Creating the FPGA Design x
2.2.1. Importing a .qptc File Generated in the Quartus® Prime Power Analyzer
3. Intel® FPGA Power and Thermal Calculator Graphical User Interface x
3.1. Intel® FPGA PTC Select Family Dialog Box 3.2. Intel® FPGA PTC Primary GUI Components 3.3. Intel® FPGA PTC - IP Wizard 3.4. Intel® FPGA PTC Searchable Drop-Down Lists 3.5. Deleting Rows from Data Entry Pages 3.6. Finding Resources Using the Find Dialog Box
3.2. Intel® FPGA PTC Primary GUI Components x
3.2.1. Intel® FPGA PTC Data Entry Pages 3.2.2. Intel® FPGA PTC Design Hierarchy 3.2.3. Intel® FPGA PTC IP Power Summary 3.2.4. Intel® FPGA PTC Field Types 3.2.5. Intel® FPGA PTC Data Entry Error Messages
3.2.2. Intel® FPGA PTC Design Hierarchy x
3.2.2.1. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator 3.2.2.2. Entering Hierarchy Information Into the Intel® FPGA PTC 3.2.2.3. Exporting, Importing, Duplicating, Renaming, and Deleting Hierarchies in the Intel® FPGA PTC 3.2.2.4. Bulk Editing Hierarchies in the Intel FPGA PTC
3.2.4. Intel® FPGA PTC Field Types x
3.2.4.1. Intel® FPGA PTC Input Field Dependencies
4. Intel® FPGA Power and Thermal Calculator Pages x
4.1. Intel® FPGA PTC - Power Summary/Navigation 4.2. Intel® FPGA PTC - Common Page Elements 4.3. Intel® FPGA PTC - Main Page 4.4. Intel® FPGA PTC - Logic Page 4.5. Intel® FPGA PTC - RAM Page 4.6. Intel® FPGA PTC - DSP Page 4.7. Intel® FPGA PTC - Clock Page 4.8. Intel® FPGA PTC - PLL Page 4.9. Intel® FPGA PTC - I/O Page 4.10. Intel® FPGA PTC - Transceiver Page 4.11. Intel® FPGA PTC - HPS Page 4.12. Intel® FPGA PTC - Crypto Page 4.13. Intel FPGA PTC - NOC Page 4.14. Intel® FPGA PTC - HBM Page 4.15. Intel® FPGA PTC - Thermal Page 4.16. Intel® FPGA PTC - Report Page
4.3. Intel® FPGA PTC - Main Page x
4.3.1. Intel® FPGA PTC - Device Selection and Thermal Analysis Windows
4.10. Intel® FPGA PTC - Transceiver Page x
4.10.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
5. Factors Affecting the Accuracy of the Intel® FPGA PTC x
5.1. Toggle Rate 5.2. I/O Bank Allocation
Answers to Top FAQs
1. Overview of the Intel® FPGA Power and Thermal Calculator
2. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator
3. Intel® FPGA Power and Thermal Calculator Graphical User Interface
4. Intel® FPGA Power and Thermal Calculator Pages
5. Factors Affecting the Accuracy of the Intel® FPGA PTC
6. Intel® FPGA Power and Thermal Calculator User Guide Archive
7. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide
A. Measuring Static Power

4.9. Intel® FPGA PTC - I/O Page

Each row in the I/O data entry page of the Intel® FPGA Power and Thermal Calculator (PTC) represents a design module with I/O pins that have the same I/O standard, input termination, current strength or output termination, data rate, clock frequency, output enable static probability, and capacitive load.

The Intel® FPGA PTC assumes that you are using external termination resistors as recommended for SSTL and high-speed transceiver logic HSTL. If your design does not use external termination resistors, choose the LVTTL/ LVCMOS I/O standard with the same VCCIO and similar current strength as the terminated I/O standard.

To use on-chip termination (OCT), select the Current Strength/Output Termination option in the Intel® FPGA PTC.

The power reported for the I/O signals includes thermal and external I/O power. The total thermal power is the sum of the thermal power consumed by the device from each power rail, as shown in the following equation.

Figure 43. Total Thermal Power 
thermal power = thermal PVCCP + thermal PVCCPT + thermal PVCCIO

The following figure shows the I/O power consumption. The ICCIO power rail includes both the thermal PIO and the external PIO:

Figure 44. I/O Power Representation


The VREF pins consume minimal current (typically less than 10 μA), which is negligible when compared with the current consumed by the general purpose I/O (GPIO) pins; therefore, the Intel® FPGA PTC does not include the current for VREF pins in the calculations.

Figure 45. I/O Page of the Intel® FPGA PTC for Agilex™ FPGA Portfolio Devices


Table 18.  I/O Page Information for Agilex™ FPGA Portfolio Devices
Column Heading Description
Voltage setting for unused GPIO banks Select a value to calculate voltage of unused GPIO banks. Available values are 1.0V, 1.05V, 1.1V, 1.2V, 1.3V, 1.5V, and Power Down Unused GPIO Banks.
Note: The availability of some voltage settings depend on the device selected.
Voltage setting for unused HVIO banks Select a value to calculate voltage of unused HVIO banks.

This field applies only to Agilex™ 5 devices. Available values are 1.8V, 2.5V, 3.3V, and Power Down Unused GPIO Banks.

Entity Name Specify an entity name in this column. This is an optional value.
Full Hierarchy Name Specify the full hierarchy name for this row, with hops delimited by the pipe character (|). If this filed is left blank, this row is assigned to the root instance. Leading, trailing, and duplicate vertical bars are ignored. Leading and trailing whitespace is ignored.
Application Specify the application for this I/O row. Using this field:
  • For Agilex™ 7 E-Series, F-Series, and I-Series devices, GPIO, EMIF, and SerDes interface can be instantiated.

    For Agilex™ 7 M-Series devices, GPIO, SERDES, EMIF DDR4, DDR5, and LPDDR5 can be instantiated.

  • For Agilex™ 5 devices, GPIO, SERDES, EMIF DDR4, LPDDR4, LPDDR5, HVIO, and RGMII can be instantiated.
Bank ID The I/O bank ID for this row. A bank location can be assigned to I/O pins to change how the I/O resources are placed, affecting thermals and utilization. If one row uses more I/O resources than available in the assigned bank, resources overflow to the next available bank.
# of Instances Enter the number of SerDes channels, IO Pins or IO PHY Lanes in this module.
Interface Parameters Interface Direction Specifies the direction of pins/SerDes channels. For SerDes, the DPA mode in which the SerDes channels are operating can also be specified.
Frequency (MHz) / Data Rate (Mbps)
  • For EMIF application, this field represents the frequency of the memory clock (in MHz).
  • For GPIO Pin, this field represents the pin frequency.
  • For SerDes application, this field represents the max data rate (in Mbps).

For example, 100 MHz clock with a 12.5% toggle rate means that each IO pin toggles 12.5 million times per second (100Mhz × 12.5%)

Interface Rate Specifies the interface data rate, the clock ratio between the external interface to the FPGA.
  • For GPIO applications, this field indicates whether I/O value changes once (Single Data Rate) or twice (Double Data Rate).
  • For SerDes applications, this field represents the serialization factor, or the number of parallel data bits for each serial data bit.
  • For EMIF applications, this field only supports full-rate (1), half-rate (2), or quarter-rate (4).
Toggle % Percentage of clock cycles when the I/O signal changes value. This value is multiplied by clock frequency to determine the number of transitions per second. If DDR is selected, the toggle rate is multiplied by an additional factor of two.
Write Enable %

When Input Termination is set to OFF, enter the average percentage of time that:

  • Output I/O is enabled
  • Bidirectional I/O is an output and enabled

For EMIF applications where this field is enabled, enter the average percentage of time that the data lanes are sending write data.

Input Termination is set to ON, enter the average percentage of time that On-Chip Termination is not active.

Read Enable %

Enter the average percentage of time that:

  • Output I/O is enabled
  • Bidirectional I/O is an output and enabled

For EMIF applications where this field is enabled, enter the average percentage of time that the data lanes are receiving read data.

Note: If you are using Agilex™ 5 or Agilex™ 7 M-Series devices, you can modify this field for all applications except HVIO.
Registered Indicates whether the application is registered or not.
Memory IP Parameters DQ Width Enter the number of DQ pins in this module.
Data Lanes Enter the number of I/O lanes used as data lanes in this module. You must first specify the number of DQ pins, to enable this field.
A/C Lanes Enter the number of I/O lanes used as address/command lanes in this module.
I/O Analog Settings I/O Standard Specifies the I/O standard used by the I/O pins in this module.
Input Termination Specifies the input termination setting for the input and bidirectional pins in this module.
Current Strength/ Output Termination Specifies the current strength or output termination setting for the output and bidirectional pins in this module. Current strength and output termination are mutually exclusive.
Slew Rate Specifies the slew rate setting for the output and bidirectional pins in this module. Using a lower slew rate setting helps reduce switching noise but may increase delay.
VOD Setting Specifies the differential output voltage (VOD) for the output and bidirectional pins in the module. A smaller number indicates a smaller VOD, which reduces static power.
Programmable De-Emphasis Specifies the de-emphasis setting for the output and bidirectional pins in this module. A larger number indicates a smaller pre-emphasis, which reduces dynamic power.
Load (pF) Specifies pin loading external to the chip (in pF). Applies only to outputs and bidirectional pins. Pin and package capacitance is already included in the I/O model. Include only off-chip capacitance.
Power (W) Digital Power dissipated in the digital domain of the I/O-subsystem including GPIO, EMIF controller, and SerDes controller.
Analog Power dissipated in the analog domain of the I/O-subsystem, for example, I/O buffers.
Total Specifies the total power dissipation (in W). Sum of analog and digital power.
User Comments Enter any comments. This is an optional entry.
Figure 46. I/O Page of the Intel® FPGA PTC for Stratix® 10 Devices
Table 19.  I/O Page Information for Stratix® 10 Devices
Column Heading Description
Entity Name Specify a name for the I/O in this column. This is an optional value.
Full Hierarchy Name Specify the hierarchical path relevant to this entry. This is an optional entry. When entering levels of hierarchy, the pipe character (|) denotes a level of hierarchy.
Application Specify the application for this I/O row. GPIO and SerDes interfaces can be instantiated using this field. Use the IP Wizard to instantiate external memory interface (EMIF) interfaces.
Bank Type Specifies the type of I/O bank for this row.
  • 1P8V banks support I/O standards up to 1.8V as well as LVDS I/O standards.
  • 3VIO banks support CMOS I/O standards up to 3.0V.
  • HPS banks include dedicated HPS pins.
  • HPS-1P8V banks are similar to 1P8V banks in terms of supported I/O standards; these banks can serve as either general purpose I/Os or as EMIF interfaces in HPS applications.
DDR Rate Specifies the clock rate of PHY logic. Determines the clock frequency of PHY logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a "Quarter Rate" interface means that the PHY logic in the FPGA runs at 200MHz.
I/O Standard Specifies the I/O standard used by the I/O pins in this module.
Input Termination Specifies the input termination setting for the input and bidirectional pins in this module.
Current Strength/ Output Termination Specifies the current strength or output termination setting for the output and bidirectional pins in this module. Current strength and output termination are mutually exclusive.
Slew Rate Specifies the slew rate setting for the output and bidirectional pins in this module. Using a lower slew rate setting helps reduce switching noise but may increase delay.
VOD Setting Specifies the differential output voltage (VOD) for the output and bidirectional pins in the module. A smaller number indicates a smaller VOD, which reduces static power.
Pre-Emphasis Setting Specifies the pre-emphasis setting for the output and bidirectional pins in this module. A smaller number indicates a smaller pre-emphasis, which reduces dynamic power.
# Input Pins Specifies the number of input-only I/O pins in this module. Differential pin pairs count as one pin.
# Output Pins Specifies the number of output-only I/O pins in this module. Differential pin pairs count as one pin.
# Bidir Pins

Specifies the number of bidirectional I/O pins in this module. Differential pin pairs count as one pin.

The I/O pin is treated as an output when its output enable signal is active and is treated as an input when the output enable signal is disabled.

An I/O pin configured as a bidirectional pin, but used only as an output, consumes more power than if it were configured as an output-only pin, due to the toggling of the input buffer every time the output buffer toggles (they share a common pin).

SDR/DDR Indicates whether I/O value changes once (Single Data Rate) or twice (Double Data Rate) For GPIO and SerDes applications.
Registered Pins Indicates whether the application is registered or not.
Toggle % Percentage of clock cycles when the I/O signal changes value. This value is multiplied by clock frequency to determine the number of transitions per second. If DDR is selected, the toggle rate is multiplied by an additional factor of two.
OE %

For modules with Input Termination set to OFF, enter the average percentage of time that:

  • Output I/O is enabled
  • Bidirectional I/O is an output and enabled

During the remaining time:

  • Output I/O is tri-stated
  • Bidirectional I/O is an input

Input Termination cannot be active while the Output I/O is enabled, so for modules with Input Termination not set to OFF, enter the average percentage of time that On-Chip Termination is inactive (that is 1-percentage that the On-Chip Termination is active). This number must be a percentage between 0% and 100%.

Load (pF) Specifies pin loading external to the chip (in pF). Applies only to outputs and bidirectional pins. Pin and package capacitance is already included in the I/O model. Include only off-chip capacitance.
Pin Clock / Memory Clock Freq (MHz) Clock frequency (in MHz). For example, 100 MHz with a 12.5% toggle percentage means that each I/O pin toggles 12.5 million times per second (100 MHz * 12.5%).
Periphery Clock Freq (MHz)

The I/O subsystem internal PHY clock frequency. This is an output-only field.

  • In SerDes applications, the PHY clock frequency is a function of the SerDes rate and serialization factor.
  • In external memory interface (EMIF) applications, the PHY clock frequency is a function of the memory clock frequency and DDR rate of the EMIF IP.
VCO Clock Freq (MHz)

The internal VCO operating frequency. This is an output-only field.

  • In SerDes applications, VCO frequency is a function of SerDes Data rate.
  • In external memory interface (EMIF) applications, the VCO frequency is a function of the memory clock frequency of the EMIF IP.
  • In GPIO mode, the VCO frequency is not applicable.
LVDS SerDes Serialization Factor

Number of parallel data bits for each serial data bit. Used for SerDes-DPA.

Data Rate (Mbps) The maximum data rate of the SerDes channels in Mbps.
Mode The DPA mode in which the SerDes channels are operating.
# of Channels The number of channels running at the data rate of this SerDes domain.
Power (W) Digital Power dissipated in the digital domain of the I/O-subsystem including GPIO, EMIF controller and SerDes controller.
Analog Power dissipated in the analog domain of the I/O-subsystem, for example, I/O buffers.
Total Specifies the total power dissipation (in W). Sum of analog and digital power.
User Comments Enter any comments. This is an optional entry.

For more information about the I/O standard termination schemes, refer to I/O and High Speed I/Os in Agilex™ 7 Devices.

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