Intel® FPGA Power and Thermal Calculator User Guide

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ID 683445
Date 9/26/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Overview of the Intel® FPGA Power and Thermal Calculator 2. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator 3. Intel® FPGA Power and Thermal Calculator Graphical User Interface 4. Intel® FPGA Power and Thermal Calculator Pages 5. Factors Affecting the Accuracy of the Intel® FPGA PTC 6. Intel® FPGA Power and Thermal Calculator User Guide Archive 7. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide A. Measuring Static Power
1. Overview of the Intel® FPGA Power and Thermal Calculator x
1.1. Accessing the Intel FPGA Power and Thermal Calculators 1.2. Intel® FPGA PTC Power Model Status 1.3. Definitions of Power Terms Used in this Document
2. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator x
2.1. Estimating Power Before Starting the FPGA Design 2.2. Estimating Power While Creating the FPGA Design 2.3. Estimating Power After Completing the FPGA Design 2.4. Estimating Power for Dual-Core Devices
2.2. Estimating Power While Creating the FPGA Design x
2.2.1. Importing a .qptc File Generated in the Quartus® Prime Power Analyzer
3. Intel® FPGA Power and Thermal Calculator Graphical User Interface x
3.1. Intel® FPGA PTC Select Family Dialog Box 3.2. Intel® FPGA PTC Primary GUI Components 3.3. Intel® FPGA PTC - IP Wizard 3.4. Intel® FPGA PTC Searchable Drop-Down Lists 3.5. Deleting Rows from Data Entry Pages 3.6. Finding Resources Using the Find Dialog Box
3.2. Intel® FPGA PTC Primary GUI Components x
3.2.1. Intel® FPGA PTC Data Entry Pages 3.2.2. Intel® FPGA PTC Design Hierarchy 3.2.3. Intel® FPGA PTC IP Power Summary 3.2.4. Intel® FPGA PTC Field Types 3.2.5. Intel® FPGA PTC Data Entry Error Messages
3.2.2. Intel® FPGA PTC Design Hierarchy x
3.2.2.1. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator 3.2.2.2. Entering Hierarchy Information Into the Intel® FPGA PTC 3.2.2.3. Exporting, Importing, Duplicating, Renaming, and Deleting Hierarchies in the Intel® FPGA PTC 3.2.2.4. Bulk Editing Hierarchies in the Intel FPGA PTC
3.2.4. Intel® FPGA PTC Field Types x
3.2.4.1. Intel® FPGA PTC Input Field Dependencies
4. Intel® FPGA Power and Thermal Calculator Pages x
4.1. Intel® FPGA PTC - Power Summary/Navigation 4.2. Intel® FPGA PTC - Common Page Elements 4.3. Intel® FPGA PTC - Main Page 4.4. Intel® FPGA PTC - Logic Page 4.5. Intel® FPGA PTC - RAM Page 4.6. Intel® FPGA PTC - DSP Page 4.7. Intel® FPGA PTC - Clock Page 4.8. Intel® FPGA PTC - PLL Page 4.9. Intel® FPGA PTC - I/O Page 4.10. Intel® FPGA PTC - Transceiver Page 4.11. Intel® FPGA PTC - HPS Page 4.12. Intel® FPGA PTC - Crypto Page 4.13. Intel FPGA PTC - NOC Page 4.14. Intel® FPGA PTC - HBM Page 4.15. Intel® FPGA PTC - Thermal Page 4.16. Intel® FPGA PTC - Report Page
4.3. Intel® FPGA PTC - Main Page x
4.3.1. Intel® FPGA PTC - Device Selection and Thermal Analysis Windows
4.10. Intel® FPGA PTC - Transceiver Page x
4.10.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
5. Factors Affecting the Accuracy of the Intel® FPGA PTC x
5.1. Toggle Rate 5.2. I/O Bank Allocation
Answers to Top FAQs
1. Overview of the Intel® FPGA Power and Thermal Calculator
2. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator
3. Intel® FPGA Power and Thermal Calculator Graphical User Interface
4. Intel® FPGA Power and Thermal Calculator Pages
5. Factors Affecting the Accuracy of the Intel® FPGA PTC
6. Intel® FPGA Power and Thermal Calculator User Guide Archive
7. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide
A. Measuring Static Power

3.2.2.2. Entering Hierarchy Information Into the Intel® FPGA PTC

If you want Intel® FPGA Power and Thermal Calculator (PTC) estimation to reflect your design hierarchy, you must first enter (or import from a prior PTC session) your design's power data and hierarchy level information into the Intel® FPGA PTC data entry pages. The Intel® FPGA PTC then reports, in watts, the subtotals of the power consumed by each architectural feature, for each level of design hierarchy.

When entering levels of hierarchy in the Intel® FPGA PTC, the pipe character (|) denotes a level of hierarchy. For example, the following notation indicates three levels of hierarchy. Hierarchy a is the highest level. Hierarchy b is the second level. Hierarchy c is the third level. 

a|b|c

Instance paths may, optionally, begin with a leading pipe character (|). But regardless of whether a leading pipe is is there or not, paths are treated the same.

When you enter an entity name for a given hierarchy, the Intel® FPGA PTC automatically updates the entity name in the Design Hierarchy tab of the Hierarchy Manager and on all data-entry pages that include that hierarchy.

To enter design hierarchy information into the Intel® FPGA PTC, follow these steps:

  1. Open your version of the Intel® FPGA PTC, as Accessing the Intel FPGA Power and Thermal Calculators describes.
  2. Click the View menu and select one of the Intel® FPGA PTC pages, such as the Logic page.
    Figure 16.  Intel® FPGA PTC Logic Page


  3. In the Full Hierarchy Name cell, type the hierarchical name of a hierarchy in your design, using the pipe character (|) as the hierarchy level delimiter. For example, the following defines the b level of hierarchy that is child of hierarchy a:
    a|b
    Figure 17. Entering Full Hierarchy Name in Intel® FPGA PTC


  4. In the Entity Name cell, enter the name of the design entity. If a newly entered hierarchy name already exists in the design, the Entity Name cell is already populated. Also, changing the entity name for a particular hierarchy name changes it for all_occurrences of that hierarchy name.
  5. Specify values for the #Half ALMs, #FFs, Clock Freq. (MHz), Toggle % and Routing Factor cells for each hierarchy. Repeat appropriate entries for design hierarchies on other pages.

    The instance appears hierarchically in the Design Hierarchy in the Intel® FPGA PTC, showing the dynamic power estimate for each hierarchy level, and the cumulative power for all instances and hierarchy levels.

    Figure 18.  Intel® FPGA PTC Design Hierarchy
  6. In the Design Hierarchy, you can right-click any instance to Rename, Duplicate, or Export the Intel® FPGA PTC data for the levels of hierarchy that you define.
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