Intel® FPGA Power and Thermal Calculator User Guide

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ID 683445
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Overview of the Intel® FPGA Power and Thermal Calculator 3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator 4. Intel® FPGA Power and Thermal Calculator Graphical User Interface 5. Intel® FPGA Power and Thermal Calculator Pages 6. Factors Affecting the Accuracy of the Intel® FPGA PTC 7. Intel® FPGA Power and Thermal Calculator User Guide Archive 8. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide A. Measuring Static Power
2. Overview of the Intel® FPGA Power and Thermal Calculator x
2.1. Accessing the Intel FPGA Power and Thermal Calculators 2.2. Intel® FPGA PTC Power Model Status 2.3. Definitions of Power Terms Used in this Document
3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator x
3.1. Estimating Power Before Starting the FPGA Design 3.2. Estimating Power While Creating the FPGA Design 3.3. Estimating Power After Completing the FPGA Design 3.4. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator 3.5. Estimating Power for Dual-Core Devices
3.2. Estimating Power While Creating the FPGA Design x
3.2.1. Importing a .qptc File Generated in the Intel® Quartus® Prime Power Analyzer
3.4. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator x
3.4.1. Entering Hierarchy Information Into the Intel® FPGA PTC 3.4.2. Exporting, Importing, Duplicating, Renaming, and Deleting Hierarchies in the Intel® FPGA PTC 3.4.3. Bulk Editing Hierarchies in the Intel FPGA PTC
4. Intel® FPGA Power and Thermal Calculator Graphical User Interface x
4.1. Intel® FPGA PTC Select Family Dialog Box 4.2. Intel® FPGA PTC Primary GUI Components 4.3. Deleting Rows from Data Entry Pages 4.4. Intel® FPGA PTC - IP Wizard
4.2. Intel® FPGA PTC Primary GUI Components x
4.2.1. Intel® FPGA PTC Data Entry Pages 4.2.2. Intel® FPGA PTC Hierarchy Manager 4.2.3. Intel® FPGA PTC Field Types 4.2.4. Intel® FPGA PTC Data Entry Error Messages
4.2.3. Intel® FPGA PTC Field Types x
4.2.3.1. Intel® FPGA PTC Input Field Dependencies
5. Intel® FPGA Power and Thermal Calculator Pages x
5.1. Intel® FPGA PTC - Power Summary/Navigation 5.2. Intel® FPGA PTC - Common Page Elements 5.3. Intel® FPGA PTC - Main Page 5.4. Intel® FPGA PTC - Logic Page 5.5. Intel® FPGA PTC - RAM Page 5.6. Intel® FPGA PTC - DSP Page 5.7. Intel® FPGA PTC - Clock Page 5.8. Intel® FPGA PTC - PLL Page 5.9. Intel® FPGA PTC - I/O Page 5.10. Intel® FPGA PTC - Transceiver Page 5.11. Intel® FPGA PTC - HPS Page 5.12. Intel® FPGA PTC - Crypto Page 5.13. Intel FPGA PTC - NOC Page 5.14. Intel® FPGA PTC - HBM Page 5.15. Intel® FPGA PTC - Thermal Page 5.16. Intel® FPGA PTC - Report Page
5.3. Intel® FPGA PTC - Main Page x
5.3.1. Intel® FPGA PTC - Device Selection and Thermal Analysis Windows
5.10. Intel® FPGA PTC - Transceiver Page x
5.10.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
6. Factors Affecting the Accuracy of the Intel® FPGA PTC x
6.1. Toggle Rate 6.2. I/O Bank Allocation
1. Answers to Top FAQs
2. Overview of the Intel® FPGA Power and Thermal Calculator
3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator
4. Intel® FPGA Power and Thermal Calculator Graphical User Interface
5. Intel® FPGA Power and Thermal Calculator Pages
6. Factors Affecting the Accuracy of the Intel® FPGA PTC
7. Intel® FPGA Power and Thermal Calculator User Guide Archive
8. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide
A. Measuring Static Power

3.5. Estimating Power for Dual-Core Devices

Devices such as the Intel® Stratix® 10 1SG10M contain two core dies, and are not directly supported by the Intel® FPGA PTC. Power estimation for these devices requires a separate calculator, together with outputs from the Intel® FPGA PTC and some transceiver data.

Package Details

The device package contains two core fabric dies, each with two associated transceivers. In the figure below, U1 and U2 identify the two core fabric tiles, with HSSI_* identifying their respective transceivers.

Figure 9. Dual-core Package Layout

Generating a PTC File and Importing the Data Into the Intel® FPGA PTC

  1. In the Intel® Quartus® Prime software, generate a PTC file for your design for the U1 tile.
  2. Create a script file for U1 (for example, design_u1.epe_script) containing the following lines:
    import,<U1_name>.ptc
		export_output_fields, <U1_name>.epe_dump
  3. Generate an epe_dump file for U1, by running the following command:
    quartus_ptc --epe_test_command=runscript --epe_input=design_u1.epe_script --family=nadder
  4. Download the 1SG10M_Calculator spreadsheet from the Power Estimators and Power Analyzer page.
  5. Open the 1SG10M_Calculator spreadsheet.
  6. Import the .epe_dump file into the spreadsheet, by clicking on Data in the spreadsheet menu bar, and then selecting the From Text/CSV icon.
    Figure 10. Spreadsheet Menu Bar


  7. Select the <U1_name>.epe_dump file that you generate in step 3, and click Import.
  8. Ensure that Comma is selected in the Delimiter field, and click Load, as Specifying Comma Delimiters shows.
  9. After the .epe_dump file loads, copy all the data from the generated worksheet and paste it into the U1 worksheet, replacing any existing data there, as Newly Generated Worksheet shows.
  10. Repeat the above steps for the U2 die, as Content Copied Into U1 Worksheet shows.
Figure 11. Specifying Comma Delimiters


Figure 12. Newly Generated Worksheet


Figure 13. Content Copied into U1 Worksheet


Interpreting the Spreadsheet

The Total_power_per_rail worksheet shows the power summary for both U1 and U2 — in this case, 1SG10M as a whole device. On the Inputs worksheet, you need to provide the Ambient Temp, Max Junction Temp, TJ-MAX , and HSSI information.

Figure 14. Input Tab

The Thermal worksheet shows the summary for Ψ values and TSD offset values.

Figure 15. Thermal Worksheet
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