RapidIO II Intel® FPGA IP User Guide

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ID 683444
Date 9/28/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the RapidIO II Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Signals 6. Software Interface 7. Testbench 8. RapidIO II IP Core User Guide Archives 9. Document Revision History for the RapidIO II Intel® FPGA IP User Guide A. Initialization Sequence B. Differences Between RapidIO II IP Core and RapidIO IP Core
1. About the RapidIO II Intel® FPGA IP x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grades 1.6. Release Information
1.1. Features x
1.1.1. Supported Transactions
1.3. IP Core Verification x
1.3.1. Simulation Testing 1.3.2. Hardware Testing 1.3.3. Interoperability Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Intel® FPGA IP Evaluation Mode 2.32.4. Generating IP Cores2.32.4. Generating IP Cores 2.32.4. Generating IP Cores2.32.4. Generating IP Cores 2.5. RapidIO II IP Core Testbench Files 2.6. Simulating IP Cores 2.7. Integrating Your IP Core in Your Design 2.8. Compiling the Full Design and Programming the FPGA 2.9. Instantiating Multiple RapidIO II IP Cores in V-series FPGA devices
2.32.4. Generating IP Cores2.32.4. Generating IP Cores x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 2.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.32.4. Generating IP Cores2.32.4. Generating IP Cores x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 2.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.6. Simulating IP Cores x
2.6.1. Simulating the Testbench with the ModelSim Simulator 2.6.2. Simulating the Testbench with the VCS Simulator 2.6.3. Simulating the Testbench with the NCSim Simulator 2.6.4. Simulating the Testbench with the Xcelium Parallel Simulator
2.7. Integrating Your IP Core in Your Design x
2.7.1. Dynamic Transceiver Reconfiguration Controller 2.7.2. Transceiver PHY Reset Controller 2.7.3. Transceiver Settings 2.7.4. Adding Transceiver Analog Settings for Arria V GZ and Stratix V Variations 2.7.5. External Transceiver PLL
3. Parameter Settings x
3.1. Physical Layer Settings 3.2. Transport Layer Settings 3.3. Logical Layer Settings 3.4. Capability Registers Settings 3.5. Command and Status Registers Settings 3.6. Error Management Registers Settings
3.1. Physical Layer Settings x
3.1.1. Mode Selection 3.1.2. Data Settings 3.1.3. Transceiver Settings
3.2. Transport Layer Settings x
3.2.1. Enable 16-Bit Device ID Width 3.2.2. Enable Avalon® -ST Pass-Through Interface 3.2.3. Disable Destination ID Checking
3.3. Logical Layer Settings x
3.3.1. Maintenance Module Settings 3.3.2. Doorbell Module Settings 3.3.3. I/O Master Module Settings 3.3.4. I/O Slave Module Settings
3.4. Capability Registers Settings x
3.4.1. Device Identity CAR 3.4.2. Device Information CAR 3.4.3. Assembly Identity CAR 3.4.4. Assembly Information CAR 3.4.5. Processing Element Features CAR 3.4.6. Switch Port Information CAR 3.4.7. Switch Route Table Destination ID Limit CAR 3.4.8. Data Streaming Information CAR 3.4.9. Source Operations CAR 3.4.10. Destination Operations CAR
3.5. Command and Status Registers Settings x
3.5.1. Data Streaming Logical Layer Control CSR 3.5.2. Port General Control CSR 3.5.3. Port 0 Control CSR 3.5.4. Lane n Status 0 CSR 3.5.5. Extended Features Pointer CSR
4. Functional Description x
4.1. Interfaces 4.2. Clocking and Reset Structure 4.3. Logical Layer Interfaces 4.4. Transport Layer 4.5. Physical Layer 4.6. Error Detection and Management
4.1. Interfaces x
4.1.1. Avalon® -MM Master and Slave Interfaces 4.1.2. Avalon-ST Interface 4.1.3. RapidIO Interface
4.2. Clocking and Reset Structure x
4.2.1. Avalon System Clock 4.2.2. Reference Clock 4.2.3. Recovered Data Clock 4.2.4. Clock Rate Relationships in the RapidIO II IP Core 4.2.5. Clock Domains in Your Platform Designer System 4.2.6. Reset for RapidIO II IP Cores
4.3. Logical Layer Interfaces x
4.3.1. Register Access Interface 4.3.2. Input/Output Logical Layer Modules 4.3.3. Maintenance Module 4.3.4. Doorbell Module 4.3.5. Avalon-ST Pass-Through Interface
4.3.1. Register Access Interface x
4.3.1.1. Non-Doorbell Register Access Operations 4.3.1.2. Register Access Interface Signals
4.3.2. Input/Output Logical Layer Modules x
4.3.2.1. Input/Output Avalon-MM Master Module 4.3.2.2. Input/Output Avalon-MM Slave Module 4.3.2.3. Avalon® -MM Burstcount and Byteenable Encoding in RapidIO Packets 4.3.2.4. Input/Output Avalon® -MM Slave Module Timing Diagrams
4.3.2.1. Input/Output Avalon-MM Master Module x
4.3.2.1.1. Input/Output Avalon-MM Master Interface Signals 4.3.2.1.2. Defining the Input/Output Avalon-MM Master Address Mapping Windows 4.3.2.1.3. RapidIO Packet Data Word Pointer and Size Encoding in Avalon® -MM Transactions 4.3.2.1.4. Input/Output Avalon-MM Master Module Timing Diagrams
4.3.2.2. Input/Output Avalon-MM Slave Module x
4.3.2.2.1. Input/Output Avalon-MM Slave Interface Signals 4.3.2.2.2. Initiating Read and Write Transactions 4.3.2.2.3. Defining the Input/Output Avalon-MM Slave Address Mapping Windows 4.3.2.2.4. Input/Output Slave Translation Window Example
4.3.3. Maintenance Module x
4.3.3.1. Maintenance Interface Transactions 4.3.3.2. Maintenance Interface Signals 4.3.3.3. Initiating MAINTENANCE Read and Write Transactions 4.3.3.4. Defining the Maintenance Address Translation Windows 4.3.3.5. Responding to MAINTENANCE Read and Write Requests 4.3.3.6. Handling Port-Write Transactions 4.3.3.7. Maintenance Interface Transaction Examples 4.3.3.8. Maintenance Packet Error Handling
4.3.3.3. Initiating MAINTENANCE Read and Write Transactions x
4.3.3.3.1. IP Core Actions
4.3.3.5. Responding to MAINTENANCE Read and Write Requests x
4.3.3.5.1. IP Core Actions
4.3.3.6. Handling Port-Write Transactions x
4.3.3.6.1. IP Core Actions 4.3.3.6.2. Port-Write Transmission 4.3.3.6.3. Port-Write Reception
4.3.3.7. Maintenance Interface Transaction Examples x
4.3.3.7.1. User Sending MAINTENANCE Write Requests 4.3.3.7.2. User Receiving MAINTENANCE Write Requests 4.3.3.7.3. User Sending MAINTENANCE Read Requests and Receiving Responses 4.3.3.7.4. User Receiving MAINTENANCE Read Requests and Sending Responses
4.3.4. Doorbell Module x
4.3.4.1. Preserving Transaction Order 4.3.4.2. Doorbell Module Interface Signals 4.3.4.3. Generating a Doorbell Message 4.3.4.4. Response to a DOORBELL Request 4.3.4.5. Receiving a Doorbell Message
4.3.5. Avalon-ST Pass-Through Interface x
4.3.5.1. Transaction ID Ranges 4.3.5.2. Pass-Through Interface Signals 4.3.5.3. Pass-Through Interface Usage Examples
4.3.5.3. Pass-Through Interface Usage Examples x
4.3.5.3.1. User Sending Write Request 4.3.5.3.2. User Receiving Write Request 4.3.5.3.3. User Sending Read Request and Receiving Read Response 4.3.5.3.4. User Receiving Read Request and Sending Read Response 4.3.5.3.5. User Sending Streaming Write Request 4.3.5.3.6. User Receiving Streaming Write Request
4.4. Transport Layer x
4.4.1. Receiver 4.4.2. Transmitter
4.5. Physical Layer x
4.5.1. Low-level Interface Receiver 4.5.2. Low-Level Interface Transmitter
4.6. Error Detection and Management x
4.6.1. Physical Layer Error Management 4.6.2. Logical Layer Error Management 4.6.3. Avalon-ST Pass-Through Interface
4.6.1. Physical Layer Error Management x
4.6.1.1. Protocol Violations 4.6.1.2. Fatal Errors
4.6.2. Logical Layer Error Management x
4.6.2.1. Maintenance Avalon-MM Slave 4.6.2.2. Maintenance Avalon-MM Master 4.6.2.3. Port-Write Reception Module 4.6.2.4. Port-Write Transmission Module 4.6.2.5. Input/Output Avalon-MM Slave 4.6.2.6. Input/Output Avalon-MM Master
5. Signals x
5.1. Global Signals 5.2. Physical Layer Signals 5.3. Logical and Transport Layer Signals 5.4. Error Management Extension Signals
5.2. Physical Layer Signals x
5.2.1. Status Packet and Error Monitoring Signals 5.2.2. Low Latency Signals 5.2.3. Transceiver Signals 5.2.4. Register-Related Signals
5.2.2. Low Latency Signals x
5.2.2.1. Multicast Event Signals 5.2.2.2. Link-Request Reset-Device Signals
5.3. Logical and Transport Layer Signals x
5.3.1. Avalon-MM Interface Signals 5.3.2. Avalon® -ST Pass-Through Interface Signals 5.3.3. Data Streaming Support Signals 5.3.4. Transport Layer Packet and Error Monitoring Signal
5.3.1. Avalon-MM Interface Signals x
5.3.1.1. Register Access Interface Signals 5.3.1.2. Input/Output Avalon-MM Master Interface Signals 5.3.1.3. Input/Output Avalon-MM Slave Interface Signals 5.3.1.4. Maintenance Interface Signals 5.3.1.5. Doorbell Module Interface Signals
5.4. Error Management Extension Signals x
5.4.1. Error Reporting Signals
6. Software Interface x
6.1. Memory Map 6.2. Physical Layer Registers 6.3. Transport and Logical Layer Registers
6.1. Memory Map x
6.1.1. CAR Memory Map 6.1.2. CSR Memory Map 6.1.3. LP-Serial Extended Features Block Memory Map 6.1.4. LP-Serial Lane Extended Features Block Memory Map 6.1.5. Error Management Extensions Extended Features Block Memory Map 6.1.6. Maintenance Module Registers Memory Map 6.1.7. I/O Logical Layer Master Module Registers Memory Map 6.1.8. I/O Logical Layer Slave Module Registers Memory Map 6.1.9. Doorbell Module Registers Memory Map
6.2. Physical Layer Registers x
6.2.1. LP-Serial Extended Features Block Memory Map 6.2.2. LP-Serial Lane Extended Features Block Memory Map
6.2.1. LP-Serial Extended Features Block Memory Map x
6.2.1.1. LP-Serial Register Block Header 6.2.1.2. Port Link Time-out Control CSR 6.2.1.3. Port Response Time-out Control CSR 6.2.1.4. Port General Control CSR 6.2.1.5. Port 0 Link Maintenance Request CSR 6.2.1.6. Port 0 Link Maintenance Response CSR 6.2.1.7. Port 0 Local AckID CSR 6.2.1.8. Port 0 Control 2 CSR 6.2.1.9. Port 0 Error and Status CSR 6.2.1.10. Port 0 Control CSR
6.2.2. LP-Serial Lane Extended Features Block Memory Map x
6.2.2.1. LP-Serial Lane Register Block Header 6.2.2.2. LP-Serial Lane n Status 0 6.2.2.3. LP-Serial Lane n Status 1 6.2.2.4. LP-Serial Lane n Status 2 6.2.2.5. LP-Serial Lane n Status 3 6.2.2.6. LP-Serial Lane n Status 4
6.3. Transport and Logical Layer Registers x
6.3.1. Capability Registers (CARs) 6.3.2. Command and Status Registers (CSRs) 6.3.3. Maintenance Module Registers 6.3.4. I/O Logical Layer Master Module Registers 6.3.5. I/O Logical Layer Slave Module Registers 6.3.6. Error Management Registers 6.3.7. Doorbell Message Registers
6.3.1. Capability Registers (CARs) x
6.3.1.1. CAR Memory Map 6.3.1.2. Device Identity CAR 6.3.1.3. Device Information CAR 6.3.1.4. Assembly Identity CAR 6.3.1.5. Assembly Information CAR 6.3.1.6. Processing Element Features CAR 6.3.1.7. Switch Port Information CAR 6.3.1.8. Source Operations CAR 6.3.1.9. Destination Operations CAR 6.3.1.10. Switch Route Table Destination ID Limit CAR 6.3.1.11. Data Streaming Information CAR
6.3.2. Command and Status Registers (CSRs) x
6.3.2.1. CSR Memory Map 6.3.2.2. Data Streaming Logical Layer Control CSR 6.3.2.3. Processing Element Logical Layer Control CSR 6.3.2.4. Local Configuration Space Base Address 0 CSR 6.3.2.5. Local Configuration Space Base Address 1 CSR 6.3.2.6. Base Device ID CSR 6.3.2.7. Host Base Device ID Lock CSR 6.3.2.8. Component Tag CSR
6.3.3. Maintenance Module Registers x
6.3.3.1. Maintenance Module Registers Memory Map 6.3.3.2. Maintenance Interrupt Control Registers 6.3.3.3. Transmit Maintenance Registers 6.3.3.4. Transmit Port-Write Registers 6.3.3.5. Receive Port-Write Registers
6.3.4. I/O Logical Layer Master Module Registers x
6.3.4.1. I/O Logical Layer Master Module Registers Memory Map 6.3.4.2. I/O Master Address Mapping Registers 6.3.4.3. I/O Master Interrupts
6.3.5. I/O Logical Layer Slave Module Registers x
6.3.5.1. I/O Logical Layer Slave Module Registers Memory Map 6.3.5.2. I/O Slave Address Mapping Registers 6.3.5.3. I/O Slave Interrupts 6.3.5.4. I/O Slave Transactions and Requests
6.3.6. Error Management Registers x
6.3.6.1. Error Management Extensions Extended Features Block Memory Map 6.3.6.2. Error Management Extensions Block Header 6.3.6.3. Logical/Transport Layer Error Detect 6.3.6.4. Logical/Transport Layer Error Enable 6.3.6.5. Logical/Transport Layer Address Capture 6.3.6.6. Logical/Transport Layer Device ID Capture 6.3.6.7. Logical/Transport Layer Control Capture 6.3.6.8. Port-Write Target Device ID 6.3.6.9. Packet Time-to-Live 6.3.6.10. Port 0 Error Detect 6.3.6.11. Port 0 Error Rate Enable 6.3.6.12. Port 0 Attributes Capture 6.3.6.13. Port 0 Packet/Control Symbol Capture 0 6.3.6.14. Port 0 Packet Capture 1 6.3.6.15. Port 0 Packet Capture 2 6.3.6.16. Port 0 Packet Capture 3 6.3.6.17. Port 0 Error Rate 6.3.6.18. Port 0 Error Rate Threshold
6.3.7. Doorbell Message Registers x
6.3.7.1. Doorbell Module Registers Memory Map 6.3.7.2. Rx Doorbell 6.3.7.3. Tx Doorbell 6.3.7.4. Doorbell Interrupt
7. Testbench x
7.1. Testbench Overview 7.2. Testbench Sequence 7.3. Testbench Completion 7.4. Transceiver Level Connections in the Testbench
7.2. Testbench Sequence x
7.2.1. Reset, Initialization, and Configuration 7.2.2. Maintenance Write and Read Transactions 7.2.3. SWRITE Transactions 7.2.4. NREAD Transactions 7.2.5. NWRITE_R Transactions 7.2.6. NWRITE Transactions 7.2.7. Doorbell Transactions 7.2.8. Port-Write Transactions 7.2.9. Transactions Across the AVST Pass-Through Interface
Product Discontinuance Notification
1. About the RapidIO II Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. RapidIO II IP Core User Guide Archives
9. Document Revision History for the RapidIO II Intel® FPGA IP User Guide
A. Initialization Sequence
B. Differences Between RapidIO II IP Core and RapidIO IP Core

6.2.1.10. Port 0 Control CSR

Table 97.  Port 0 Control CSR — 0x15C
Field Bits Access Function Default
PORT_WIDTH [31:30] RO Together with the EXTENDED_PORT_WIDTH field, indicates the hardware widths this port supports in addition to the 1× (single lane) width:
  • Bit [31]: 2× (two-lane) support
    • 1’b0: This port does not support a 2× RapidIO link.
    • 1’b1: This port supports a 2× RapidIO link.
  • Bit[30]: 4× (four-lane) support
    • 1’b0: This port does not support a 4× RapidIO link.
    • 1’b1: This port supports a 4× RapidIO link.
32
INIT_WIDTH [29:27] RO Width of the port after being initialized:
  • 3'b000: Single lane port, lane 0.
  • 3'b001: Single lane port, lane R (redundancy lane).
  • 3'b010: Four-lane port.
  • 3'b011: Two-lane port.
  • 3’b100: Eight-lane port.
  • 3’b101: Sixteen-lane port.
  • 3’b110–3'b111—Reserved.
This field is reset to the largest supported port width, which can be any of 3’b000, 3’b010, and 3’b011, based on your selection in the RapidIO II parameter editor. 		32
PWIDTH_OVRIDE [26:24] RW Together with the EXTENDED_PWIDTH_OVRIDE field (bits [15:14]), indicates soft port configuration to control the width modes available for port initialization.
  • When bit [26] has the value of 1’b0, bits [15:14] are Reserved.
  • When bit [26] has the value of 1’b1:
    • Bit [25] is the Enable bit for 4× mode.
    • Bit [24] is the Enable bit for 2× mode.
    • Bit [15] is the Enable bit for 8× mode.
    • Bit [14] is the Enable bit for 16× mode.
The RapidIO II IP core supports the following valid values for (PWIDTH_OVRIDE,EXTENDED_PWIDTH_OVRIDE):
  • 5'b000xx—All lane widths that the port supports are enabled.
  • 5'b010xx—Force single lane, lane R not forced.
  • 5'b011xx—Force single lane, force lane R.
  • 5'b10100—2× mode is enabled, 4× mode is disabled.
  • 5’b11000—4× mode is enabled, 2× mode is disabled.
  • 5'b11100—2× and 4× modes are enabled.
All other values are Reserved. When the value in the PWIDTH_OVRIDE or EXTENDED_PWIDTH_OVRIDE field changes, the port re-initializes using the new field values. 		3'b000
PORT_DIS [23] RW Port disable:
  • 'b0—Port receivers/drivers are enabled.
  • 'b1—Port receivers are disabled and are unable to receive or transmit any packets or control symbols.
While this bit is set, the initialization state machines force_reinit signal is asserted. This assertion forces the port to the SILENT state 		1'b0
OUT_PENA [22] RW Output port transmit enable:
  • 'b0—Port is stopped and not enabled to issue any packets except to route or respond to I/O logical MAINTENANCE packets. Control symbols are not affected and are sent normally.
  • 'b1—Port is enabled to issue packets.
The value in the PORT_LOCKOUT field (bit [1] of this register) can override the values in the OUT_PENA and IN_PENA fields 		1'b0
IN_PENA [21] RW Input port receive enable:
  • 'b0—Port is stopped and only enabled to respond to I/O Logical MAINTENANCE requests. Other requests return packet-not-accepted control symbols to force an error condition to be signaled by the sending device. However, the IP core still handles normally any control symbols it receives.
  • 'b1—Port is enabled to respond to any packet.
The value in the PORT_LOCKOUT field (bit [1] of this register) can override the values in the OUT_PENA and IN_PENA fields. 		1'b0
ERR_CHK_DIS [20] RO This bit enables (1’b0) or disables (1’b1) all RapidIO transmission error checking. The RapidIO II IP core does not support the disabling of error checking and recovery, so this bit always has the value of 1’b0. 1'b0
Multicast-event Participant [19] RW Indicates that the system should send incoming Multicast-event control symbols to this port (multiple port devices only). 1'b1
Flow Control Participant [18] RW Enables or disables flow control transactions:
  • 1’b0: Do not route or issue flow control transactions to this port.
  • 1’b1: Route or issue flow control transactions to this port.
This field does not affect the IP core configuration. 		32
Enumeration Boundary [17] RW Indicates whether this port should delimit enumeration. Any enumeration boundary aware system enumeration algorithm should honor this flag. The algorithm, on either the Rx port or the Tx port, should not enumerate past a port in which this bit is set to the value of 1’b1. This field supports software-enforced enumeration domains in the RapidIO network. 32
Flow Arbitration Participant [16] RW Enables or disables flow arbitration transactions:
  • 1’b0: Do not route or issue flow arbitration transactions to this port.
  • 1’b1: Route or issue flow arbitration transactions to this port.
32
EXTENDED_PWIDTH_ OVRIDE [15:14] RW Together with the PWIDTH_OVRIDE field (bits [26:24] of this register), indicates soft port configuration to control the width modes available for port initialization. Refer to the description of the PWIDTH_OVRIDE field. 2'b0
EXTENDED_PORT_ WIDTH [13:12] RO Together with the PORT_WIDTH field, indicates the hardware widths this port supports:
  • Bit [13]: 8× support
    • 1’b0: This port does not support a 8× RapidIO link.
    • 1’b1: This port supports a 8× RapidIO link.
  • Bit[12]: 16× support
    • 1’b0: This port does not support a 16× RapidIO link.
    • 1’b1: This port supports a 16× RapidIO link.
The RapidIO II IP core does not support 8-lane or 16-lane variations, so this field is always set to 2’b00. 		2'b0
RSRV [11:9] RO Reserved. 3'b0
DIS_DEST_ID_CHK [8] RO This bit determines whether the RapidIO II IP core checks destination IDs in incoming request packets, or promiscuously accepts all incoming request packets with a supported ftype. The reset value is set in the RapidIO II parameter editor.
  • 1'b0: Check Destination ID.
  • 1'b1: Disable Destination ID checking.
 32
LOG_TRANS_ERR_IRQ _EN [7] RW Controls whether an interrupt is generated when the logical_transport_error input signal changes from the value of 0 to the value of 1. 1'b0
PORT_ERR_IRQ_EN [6] RW Controls whether an interrupt is generated when an error is flagged in the Port 0 Error Detect register at offset 0x340. If this bit has the value of 1, an interrupt is generated when any enabled error is flagged in the Port 0 Error Detect register. 1'b0
PORT_FAIL_IRQ_EN [5] RW Controls whether an interrupt is generated when the port_failed input signal changes from the value of 0 to the value of 1. 1'b0
PORT_DEGR_IRQ_EN [4] RW Controls whether an interrupt is generated when the port_degraded input signal changes from the value of 0 to the value of 1. 1'b0
STOP_ON_PRT_FAIL_ ENCOUNTER_ENABLE [3] RW Together with the DROP_PKT_ENABLE field, specifies the behavior of the port when the failed error threshold in the Port 0 Error Rate Threshold register (offset 0x36C) has been reached or exceeded. The RapidIO II IP core supports the following valid values for (STOP_ON_PRT_FAIL_ENCOUNTER_ENABLE, DROP_PKT_ENABLE):
  • 2'b00: The port continues to attempt to transmit packets to the RapidIO link partner.
  • 2'b01: The port discards packets that receive a packet-not-accepted response. When the port discards a packet, it sets the OUT_PKT_DROPD bit in the Port 0 Error and Status CSR (offset 0x158). The port resumes normal operation when the value in the Error Rate Counter field of the Port 0 Error Rate CSR (offset 0x368) falls below the failed error threshold. This value is valid only for switch devices.
  • 2’b10: The port stops trying to send packets to the link partner, until software resets the OUT_FAIL_ENC field of the Port 0 Error and Status CSR (offset 0x158). The IP core does apply backpressure to ensure the queues do not overflow.
  • 2’b11: The port discards all output packets, until software resets the OUT_FAIL_ENC field of the Port 0 Error and Status CSR (offset 0x158). When the port discards a packet, it sets the OUT_PKT_DROPD bit in the Port 0 Error and Status CSR.
1'b0
DROP_PKT_ENABLE [2] RW Together with the STOP_ON_PRT_FAIL_ENCOUNTER_ENABLE field, specifies the behavior of the port when the failed error threshold in the Port 0 Error Rate Threshold register (offset 0x36C) has been reached or exceeded. Refer to the description of the STOP_ON_PRT_FAIL_ENCOUNTER_ENABLE field. 1'b0
PORT_LOCKOUT [1] RW This bit indicates whether the port is stopped or the IN_PENA (bit [21]) and OUT_PENA (bit [22]) register fields control the port:
  • 1'b0—The Input Port Enable (IN_PENA) and Output Port Enable (OUT_PENA) fields in this register control which packets the port may receive and transmit on the RapidIO link.
  • 1'b1—Port is stopped and is not enabled to issue or receive any packets. The input port can still follow the training procedure and can still send and respond to link-requests. All received packets return packet-not-accepted control symbols to force an error condition to be signaled by the sending device.
1'b0
PORT_TYPE [0] RO Indicates the port type, parallel or serial.
  • 1'b0: Parallel port.
  • 1'b1: Serial port.
The RapidIO II IP core supports only serial ports, so this bit always has the value of 1’b1. 		1'b1
32 Reflects the selection made in the RapidIO II parameter editor.
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