RapidIO II Intel® FPGA IP User Guide

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ID 683444
Date 9/28/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the RapidIO II Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Signals 6. Software Interface 7. Testbench 8. RapidIO II IP Core User Guide Archives 9. Document Revision History for the RapidIO II Intel® FPGA IP User Guide A. Initialization Sequence B. Differences Between RapidIO II IP Core and RapidIO IP Core
1. About the RapidIO II Intel® FPGA IP x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grades 1.6. Release Information
1.1. Features x
1.1.1. Supported Transactions
1.3. IP Core Verification x
1.3.1. Simulation Testing 1.3.2. Hardware Testing 1.3.3. Interoperability Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Intel® FPGA IP Evaluation Mode 2.32.4. Generating IP Cores2.32.4. Generating IP Cores 2.32.4. Generating IP Cores2.32.4. Generating IP Cores 2.5. RapidIO II IP Core Testbench Files 2.6. Simulating IP Cores 2.7. Integrating Your IP Core in Your Design 2.8. Compiling the Full Design and Programming the FPGA 2.9. Instantiating Multiple RapidIO II IP Cores in V-series FPGA devices
2.32.4. Generating IP Cores2.32.4. Generating IP Cores x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 2.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.32.4. Generating IP Cores2.32.4. Generating IP Cores x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 2.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.6. Simulating IP Cores x
2.6.1. Simulating the Testbench with the ModelSim Simulator 2.6.2. Simulating the Testbench with the VCS Simulator 2.6.3. Simulating the Testbench with the NCSim Simulator 2.6.4. Simulating the Testbench with the Xcelium Parallel Simulator
2.7. Integrating Your IP Core in Your Design x
2.7.1. Dynamic Transceiver Reconfiguration Controller 2.7.2. Transceiver PHY Reset Controller 2.7.3. Transceiver Settings 2.7.4. Adding Transceiver Analog Settings for Arria V GZ and Stratix V Variations 2.7.5. External Transceiver PLL
3. Parameter Settings x
3.1. Physical Layer Settings 3.2. Transport Layer Settings 3.3. Logical Layer Settings 3.4. Capability Registers Settings 3.5. Command and Status Registers Settings 3.6. Error Management Registers Settings
3.1. Physical Layer Settings x
3.1.1. Mode Selection 3.1.2. Data Settings 3.1.3. Transceiver Settings
3.2. Transport Layer Settings x
3.2.1. Enable 16-Bit Device ID Width 3.2.2. Enable Avalon® -ST Pass-Through Interface 3.2.3. Disable Destination ID Checking
3.3. Logical Layer Settings x
3.3.1. Maintenance Module Settings 3.3.2. Doorbell Module Settings 3.3.3. I/O Master Module Settings 3.3.4. I/O Slave Module Settings
3.4. Capability Registers Settings x
3.4.1. Device Identity CAR 3.4.2. Device Information CAR 3.4.3. Assembly Identity CAR 3.4.4. Assembly Information CAR 3.4.5. Processing Element Features CAR 3.4.6. Switch Port Information CAR 3.4.7. Switch Route Table Destination ID Limit CAR 3.4.8. Data Streaming Information CAR 3.4.9. Source Operations CAR 3.4.10. Destination Operations CAR
3.5. Command and Status Registers Settings x
3.5.1. Data Streaming Logical Layer Control CSR 3.5.2. Port General Control CSR 3.5.3. Port 0 Control CSR 3.5.4. Lane n Status 0 CSR 3.5.5. Extended Features Pointer CSR
4. Functional Description x
4.1. Interfaces 4.2. Clocking and Reset Structure 4.3. Logical Layer Interfaces 4.4. Transport Layer 4.5. Physical Layer 4.6. Error Detection and Management
4.1. Interfaces x
4.1.1. Avalon® -MM Master and Slave Interfaces 4.1.2. Avalon-ST Interface 4.1.3. RapidIO Interface
4.2. Clocking and Reset Structure x
4.2.1. Avalon System Clock 4.2.2. Reference Clock 4.2.3. Recovered Data Clock 4.2.4. Clock Rate Relationships in the RapidIO II IP Core 4.2.5. Clock Domains in Your Platform Designer System 4.2.6. Reset for RapidIO II IP Cores
4.3. Logical Layer Interfaces x
4.3.1. Register Access Interface 4.3.2. Input/Output Logical Layer Modules 4.3.3. Maintenance Module 4.3.4. Doorbell Module 4.3.5. Avalon-ST Pass-Through Interface
4.3.1. Register Access Interface x
4.3.1.1. Non-Doorbell Register Access Operations 4.3.1.2. Register Access Interface Signals
4.3.2. Input/Output Logical Layer Modules x
4.3.2.1. Input/Output Avalon-MM Master Module 4.3.2.2. Input/Output Avalon-MM Slave Module 4.3.2.3. Avalon® -MM Burstcount and Byteenable Encoding in RapidIO Packets 4.3.2.4. Input/Output Avalon® -MM Slave Module Timing Diagrams
4.3.2.1. Input/Output Avalon-MM Master Module x
4.3.2.1.1. Input/Output Avalon-MM Master Interface Signals 4.3.2.1.2. Defining the Input/Output Avalon-MM Master Address Mapping Windows 4.3.2.1.3. RapidIO Packet Data Word Pointer and Size Encoding in Avalon® -MM Transactions 4.3.2.1.4. Input/Output Avalon-MM Master Module Timing Diagrams
4.3.2.2. Input/Output Avalon-MM Slave Module x
4.3.2.2.1. Input/Output Avalon-MM Slave Interface Signals 4.3.2.2.2. Initiating Read and Write Transactions 4.3.2.2.3. Defining the Input/Output Avalon-MM Slave Address Mapping Windows 4.3.2.2.4. Input/Output Slave Translation Window Example
4.3.3. Maintenance Module x
4.3.3.1. Maintenance Interface Transactions 4.3.3.2. Maintenance Interface Signals 4.3.3.3. Initiating MAINTENANCE Read and Write Transactions 4.3.3.4. Defining the Maintenance Address Translation Windows 4.3.3.5. Responding to MAINTENANCE Read and Write Requests 4.3.3.6. Handling Port-Write Transactions 4.3.3.7. Maintenance Interface Transaction Examples 4.3.3.8. Maintenance Packet Error Handling
4.3.3.3. Initiating MAINTENANCE Read and Write Transactions x
4.3.3.3.1. IP Core Actions
4.3.3.5. Responding to MAINTENANCE Read and Write Requests x
4.3.3.5.1. IP Core Actions
4.3.3.6. Handling Port-Write Transactions x
4.3.3.6.1. IP Core Actions 4.3.3.6.2. Port-Write Transmission 4.3.3.6.3. Port-Write Reception
4.3.3.7. Maintenance Interface Transaction Examples x
4.3.3.7.1. User Sending MAINTENANCE Write Requests 4.3.3.7.2. User Receiving MAINTENANCE Write Requests 4.3.3.7.3. User Sending MAINTENANCE Read Requests and Receiving Responses 4.3.3.7.4. User Receiving MAINTENANCE Read Requests and Sending Responses
4.3.4. Doorbell Module x
4.3.4.1. Preserving Transaction Order 4.3.4.2. Doorbell Module Interface Signals 4.3.4.3. Generating a Doorbell Message 4.3.4.4. Response to a DOORBELL Request 4.3.4.5. Receiving a Doorbell Message
4.3.5. Avalon-ST Pass-Through Interface x
4.3.5.1. Transaction ID Ranges 4.3.5.2. Pass-Through Interface Signals 4.3.5.3. Pass-Through Interface Usage Examples
4.3.5.3. Pass-Through Interface Usage Examples x
4.3.5.3.1. User Sending Write Request 4.3.5.3.2. User Receiving Write Request 4.3.5.3.3. User Sending Read Request and Receiving Read Response 4.3.5.3.4. User Receiving Read Request and Sending Read Response 4.3.5.3.5. User Sending Streaming Write Request 4.3.5.3.6. User Receiving Streaming Write Request
4.4. Transport Layer x
4.4.1. Receiver 4.4.2. Transmitter
4.5. Physical Layer x
4.5.1. Low-level Interface Receiver 4.5.2. Low-Level Interface Transmitter
4.6. Error Detection and Management x
4.6.1. Physical Layer Error Management 4.6.2. Logical Layer Error Management 4.6.3. Avalon-ST Pass-Through Interface
4.6.1. Physical Layer Error Management x
4.6.1.1. Protocol Violations 4.6.1.2. Fatal Errors
4.6.2. Logical Layer Error Management x
4.6.2.1. Maintenance Avalon-MM Slave 4.6.2.2. Maintenance Avalon-MM Master 4.6.2.3. Port-Write Reception Module 4.6.2.4. Port-Write Transmission Module 4.6.2.5. Input/Output Avalon-MM Slave 4.6.2.6. Input/Output Avalon-MM Master
5. Signals x
5.1. Global Signals 5.2. Physical Layer Signals 5.3. Logical and Transport Layer Signals 5.4. Error Management Extension Signals
5.2. Physical Layer Signals x
5.2.1. Status Packet and Error Monitoring Signals 5.2.2. Low Latency Signals 5.2.3. Transceiver Signals 5.2.4. Register-Related Signals
5.2.2. Low Latency Signals x
5.2.2.1. Multicast Event Signals 5.2.2.2. Link-Request Reset-Device Signals
5.3. Logical and Transport Layer Signals x
5.3.1. Avalon-MM Interface Signals 5.3.2. Avalon® -ST Pass-Through Interface Signals 5.3.3. Data Streaming Support Signals 5.3.4. Transport Layer Packet and Error Monitoring Signal
5.3.1. Avalon-MM Interface Signals x
5.3.1.1. Register Access Interface Signals 5.3.1.2. Input/Output Avalon-MM Master Interface Signals 5.3.1.3. Input/Output Avalon-MM Slave Interface Signals 5.3.1.4. Maintenance Interface Signals 5.3.1.5. Doorbell Module Interface Signals
5.4. Error Management Extension Signals x
5.4.1. Error Reporting Signals
6. Software Interface x
6.1. Memory Map 6.2. Physical Layer Registers 6.3. Transport and Logical Layer Registers
6.1. Memory Map x
6.1.1. CAR Memory Map 6.1.2. CSR Memory Map 6.1.3. LP-Serial Extended Features Block Memory Map 6.1.4. LP-Serial Lane Extended Features Block Memory Map 6.1.5. Error Management Extensions Extended Features Block Memory Map 6.1.6. Maintenance Module Registers Memory Map 6.1.7. I/O Logical Layer Master Module Registers Memory Map 6.1.8. I/O Logical Layer Slave Module Registers Memory Map 6.1.9. Doorbell Module Registers Memory Map
6.2. Physical Layer Registers x
6.2.1. LP-Serial Extended Features Block Memory Map 6.2.2. LP-Serial Lane Extended Features Block Memory Map
6.2.1. LP-Serial Extended Features Block Memory Map x
6.2.1.1. LP-Serial Register Block Header 6.2.1.2. Port Link Time-out Control CSR 6.2.1.3. Port Response Time-out Control CSR 6.2.1.4. Port General Control CSR 6.2.1.5. Port 0 Link Maintenance Request CSR 6.2.1.6. Port 0 Link Maintenance Response CSR 6.2.1.7. Port 0 Local AckID CSR 6.2.1.8. Port 0 Control 2 CSR 6.2.1.9. Port 0 Error and Status CSR 6.2.1.10. Port 0 Control CSR
6.2.2. LP-Serial Lane Extended Features Block Memory Map x
6.2.2.1. LP-Serial Lane Register Block Header 6.2.2.2. LP-Serial Lane n Status 0 6.2.2.3. LP-Serial Lane n Status 1 6.2.2.4. LP-Serial Lane n Status 2 6.2.2.5. LP-Serial Lane n Status 3 6.2.2.6. LP-Serial Lane n Status 4
6.3. Transport and Logical Layer Registers x
6.3.1. Capability Registers (CARs) 6.3.2. Command and Status Registers (CSRs) 6.3.3. Maintenance Module Registers 6.3.4. I/O Logical Layer Master Module Registers 6.3.5. I/O Logical Layer Slave Module Registers 6.3.6. Error Management Registers 6.3.7. Doorbell Message Registers
6.3.1. Capability Registers (CARs) x
6.3.1.1. CAR Memory Map 6.3.1.2. Device Identity CAR 6.3.1.3. Device Information CAR 6.3.1.4. Assembly Identity CAR 6.3.1.5. Assembly Information CAR 6.3.1.6. Processing Element Features CAR 6.3.1.7. Switch Port Information CAR 6.3.1.8. Source Operations CAR 6.3.1.9. Destination Operations CAR 6.3.1.10. Switch Route Table Destination ID Limit CAR 6.3.1.11. Data Streaming Information CAR
6.3.2. Command and Status Registers (CSRs) x
6.3.2.1. CSR Memory Map 6.3.2.2. Data Streaming Logical Layer Control CSR 6.3.2.3. Processing Element Logical Layer Control CSR 6.3.2.4. Local Configuration Space Base Address 0 CSR 6.3.2.5. Local Configuration Space Base Address 1 CSR 6.3.2.6. Base Device ID CSR 6.3.2.7. Host Base Device ID Lock CSR 6.3.2.8. Component Tag CSR
6.3.3. Maintenance Module Registers x
6.3.3.1. Maintenance Module Registers Memory Map 6.3.3.2. Maintenance Interrupt Control Registers 6.3.3.3. Transmit Maintenance Registers 6.3.3.4. Transmit Port-Write Registers 6.3.3.5. Receive Port-Write Registers
6.3.4. I/O Logical Layer Master Module Registers x
6.3.4.1. I/O Logical Layer Master Module Registers Memory Map 6.3.4.2. I/O Master Address Mapping Registers 6.3.4.3. I/O Master Interrupts
6.3.5. I/O Logical Layer Slave Module Registers x
6.3.5.1. I/O Logical Layer Slave Module Registers Memory Map 6.3.5.2. I/O Slave Address Mapping Registers 6.3.5.3. I/O Slave Interrupts 6.3.5.4. I/O Slave Transactions and Requests
6.3.6. Error Management Registers x
6.3.6.1. Error Management Extensions Extended Features Block Memory Map 6.3.6.2. Error Management Extensions Block Header 6.3.6.3. Logical/Transport Layer Error Detect 6.3.6.4. Logical/Transport Layer Error Enable 6.3.6.5. Logical/Transport Layer Address Capture 6.3.6.6. Logical/Transport Layer Device ID Capture 6.3.6.7. Logical/Transport Layer Control Capture 6.3.6.8. Port-Write Target Device ID 6.3.6.9. Packet Time-to-Live 6.3.6.10. Port 0 Error Detect 6.3.6.11. Port 0 Error Rate Enable 6.3.6.12. Port 0 Attributes Capture 6.3.6.13. Port 0 Packet/Control Symbol Capture 0 6.3.6.14. Port 0 Packet Capture 1 6.3.6.15. Port 0 Packet Capture 2 6.3.6.16. Port 0 Packet Capture 3 6.3.6.17. Port 0 Error Rate 6.3.6.18. Port 0 Error Rate Threshold
6.3.7. Doorbell Message Registers x
6.3.7.1. Doorbell Module Registers Memory Map 6.3.7.2. Rx Doorbell 6.3.7.3. Tx Doorbell 6.3.7.4. Doorbell Interrupt
7. Testbench x
7.1. Testbench Overview 7.2. Testbench Sequence 7.3. Testbench Completion 7.4. Transceiver Level Connections in the Testbench
7.2. Testbench Sequence x
7.2.1. Reset, Initialization, and Configuration 7.2.2. Maintenance Write and Read Transactions 7.2.3. SWRITE Transactions 7.2.4. NREAD Transactions 7.2.5. NWRITE_R Transactions 7.2.6. NWRITE Transactions 7.2.7. Doorbell Transactions 7.2.8. Port-Write Transactions 7.2.9. Transactions Across the AVST Pass-Through Interface
Product Discontinuance Notification
1. About the RapidIO II Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. RapidIO II IP Core User Guide Archives
9. Document Revision History for the RapidIO II Intel® FPGA IP User Guide
A. Initialization Sequence
B. Differences Between RapidIO II IP Core and RapidIO IP Core

9. Document Revision History for the RapidIO II Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2020.09.28 20.3 19.2.0
  • Added Product Discontinuance Notice.
  • Added IP version information.
2018.09.21 18.0 18.0 Clarified that testbench generated from the Generate Testbench System does not have the correct connections and does not exercise the RapidIO II IP core.
2018.05.07 18.0 18.0
  • Renamed the document as RapidIO II Intel® FPGA IP User Guide.
  • Added support for Intel® Cyclone® 10 GX devices.
  • Added support for Cadence Xcelium Parallel simulator.
Date Changes
December 2017 Corrected the bit width of the signal gen_rx_pd_empty to 4-bit in Pass-Through Interface Usage Examples section.
November 2017
  • Intel® Stratix® 10 devices are now supported in the 17.1 Intel® Quartus® Prime software.
  • Updated the resource utilization metrics for Intel® Stratix® 10 (L-Tile/H-Tile) and Intel® Arria® 10 devices in Table: RapidIO II IP Core FPGA Resource Utilization.
  • Added new parameter Transceiver Tile in Table: Transceiver Settings.
  • Added support for Cadence NCSim simulator.
  • Corrected bit assignment of xamsbs[1:0]field from [17:16] to [33:32] in Table: SWRITE Request Receive Example: RapidIO Header Fields in gen_rx_hd_data Bus.
May 2017
  • Added the device support level for Arria® V (ST/SX) variations in Table: Device Family Support.
  • Updated the resource utilization metrics for all devices in Table: RapidIO II IP Core FPGA Resource Utilization.
  • Updated the procedure for Generating IP Cores using the Intel® Quartus® Prime Pro Edition 17.0 software.
  • Corrected Figure: IP Core Generation Output ( Intel® Quartus® Prime Pro Edition).
  • Changed the topic title from Specific Instructions for RapidIO II IP Core to RapidIO II IP Core Testbench Files.
  • Corrected the testbench and simulation files location for the IP variations generated using the Platform Designer IP Catalog in RapidIO II IP Core Testbench Files.
  • Added commands to Simulate the Testbench with the ModelSim Simulator for V-series device variations using the Platform Designer IP Catalog.
  • Updated the location of the HDL code for an ATX PLL in External Transceiver PLL.
  • Added the location of the HDL code for a Transceiver PHY Reset Controller in Transceiver PHY Reset Controller.
  • Added device & software support information in Table: Transceiver Settings.
  • Editorial modifications.
December 2016
  • Updated the device support level for Intel® Arria® 10 device family in Table: Device Family Support.
  • Updated the resource utilization metrics for Intel® Stratix® 10 devices in Table: RapidIO II IP Core FPGA Resource Utilization.
  • Added commands for Intel® Stratix® 10 variations to simulate the testbench with ModelSim Simulator.
  • Dynamic reconfiguration support is now available for Intel® Stratix® 10 devices.
  • Added Transceiver Share reconfiguration interface, Enable transceiver Altera Debug Master Endpoint (ADME) and VCCR_GXB and VCCT_GXB supply voltage for the transceivers parameters in Table: Transceiver Settings.

  • Corrected the specific_header Format on gen_tx_data and gen_rx_data Bus for ftype 6.

October 2016 Implemented the Intel rebranding.
August 2016 (Stratix 10 Edition Beta Release)
  • Added the Intel® Stratix® 10 device support in Table: Device Family Support.
  • Added the Intel® Stratix® 10 device performance and resource utilization (preliminary) in Table: RapidIO II IP Core FPGA Resource Utilization.
  • Added the Intel® Stratix® 10 device speed grades and maximum baud rate.
  • Added the Intel® Stratix® 10 device support in Table: Device Family Support.
  • Added the following reset signals for Intel® Stratix® 10 devices:
    • tx_digitalreset_stat
    • rx_digitalreset_stat
    • tx_analogreset_stat
    • rx_analogreset_stat
May 2016
  • Added a note to the Table: Recommended Device Family and Speed Grades to clarify speed grade support for Arria® V devices.
  • Corrected the Payload Size value for all the Maintenance Interface Transactions.
  • Stated appropriate TOP_LEVEL_NAME for both Intel® Quartus® Prime Pro and Standard edition software.
  • Corrected the timing diagrams for Avalon® -ST Pass-Through Interface Usage Examples:
    • NWRITE Transmit Example
    • NREAD Request Send and Response Receive Example
    • NREAD Request Receive and Response Send Example
    • SWRITE Transmit Example
  • Editorial modifications.
July 2015
  • Updated the descriptions of the <Gbaud>_GB_SUPPORT and <Gbaud>_GB_ENABLE fields of the Port 0 Control 2 CSR at offset 0x154.
  • Added new io_error_response_set error management extensions input signal.
  • Updated description of fields in Port 0 Control CSR at offset 0x15C.
    • Added new field PORT_ERR_IRQ_EN at bit [6].
    • Moved DIS_DEST_ID_CHK field from bit [7] to bit [8].
    • Moved LOG_TRANS_ERR_IRQ_EN field from bit [6] to bit [7].
  • Corrected description of ERR_RATE_COUNTER field of Port 0 Error Rate CSR at offset 0x368 to indicate that if the IP core detects an error in a control symbol, the counter might increment twice.
  • Clarified that the generic instructions to generate the testbench by clicking Generate > Generate Testbench in the RapidIO II parameter editor do not apply to this IP core.
  • Added information about required parameter value change for Transceiver PHY Reset Controller that connects to the RapidIO II IP core.
  • Added note in Clocking and Reset Structure to confirm the RapidIO II IP core can handle a difference of ±200PPM in the transmit clock (tx_clkout) and the recovered data clock (rx_clkout), as required by the RapidIO Interconnect Specification v2.2. Added note in Reference Clock to clarify the design requirement sufficient to ensure the ±200PPM difference limit.
  • Corrected Doorbell Message Registers offsets .
  • Corrected Error Management Registers offsets
August 2014
  • Added support for Intel® Arria® 10 devices:
    • New parameter Enable transceiver dynamic reconfiguration allows you to hide or make visible the Intel® Arria® 10 Native PHY IP core dynamic reconfiguration interface, an Avalon® -MM interface for programming the hard registers in the Intel® Arria® 10 transceiver.
    • New requirement to include TX PLL IP core in the design. New individual transceiver channel clock signals added to RapidIO II IP core to connect to an ATX PLL to support PLL sharing across the transceiver block.
    • Removed pll_locked and pll_powerdown signals from RapidIO II IP core that targets an Intel® Arria® 10 device.
  • Updated Appendix Initialization Sequence to clarify that it addresses initialization of RapidIO II IP cores rather than RapidIO IP cores. The initialization sequence is identical for the two IP cores.
June 2014
  • Modified Chapter Getting Started to describe the Intel® Quartus® Prime software v14.0 IP Catalog.
  • Modified Chapter Parameter Settings to document the new location of the Extended features pointer parameter in the RapidIO II parameter editor. The Extended features pointer parameter is now on the Command and Status Registers tab instead of the Capability Registers tab. This change dates from the Intel® Quartus® Prime software v13.1.
  • Changed bit range of ext_mnt_address from [23:2] to [21:0] and explained the address is a word address.
  • Explained that drbell_s_address is a word address and ios_rd_wr_address is a quad-word address respectively.
  • Changed bit range of mnt_s_address from [25:2] to [23:0].
  • Clarified that generating this IP core does not generate an Intel® -provided VHDL testbench, only a Verilog HDL testbench.
  • Clarified in description of ERR_RATE_COUNTER field of the Port 0 Error Rate CSR (offset 0x386).
  • Clarified that Avalon® -ST pass-through interface gen_tx_valid signal must be continuously asserted from the assertion of gen_tx_startofpacket until the deassertion of gen_tx_endofpacket.
  • Added Table specific_header Format on gen_tx_data Bus, which list header information format in gen_tx_data for all supported transaction types and both device ID widths.
  • Added four new Avalon® -ST pass-through interface usage examples, including examples with device ID width 8.
  • Corrected descriptions of IN_ERR_STOP and OUT_ERR_STOP fields of the Port 0 Error and Status CSR (offset 0x158).
  • Replaced “Serial RapidIO” with “RapidIO”. The RapidIO II IP core supports only the Serial RapidIO specification.
  • Clarified description in Table Link-Request Reset-Device Signals.
  • Corrected descriptions of OUTBOUND_ACKID and OUTSTANDING_ACKID fields of the Port 0 Local AckID CSR (0x148).
February 2013
  • Added device programming (Programming Object File (.pof) support) for Arria® V devices.
  • Added support for Arria® V GZ devices.
  • Added support for Cyclone® V devices. Cyclone® V GT devices support rates up to 5.0 Gbaud, and other Cyclone® V devices support rates up to 3.125 Gbaud.
  • Clarified in Adding Transceiver Analog Settings that this procedure is required only for Arria® V GZ and Stratix® V devices.
  • Corrected erroneous statement that software can reset the REMOTE_TX_EMPH_ENABLE bit in the Port 0 Control 2 CSR (offset 0x154).
  • Corrected the description of PORT_ERR field of Port 0 Error and Status CSR (offset 0x158).
  • Added information to the description of the Logical/Transport Layer Address Capture CSR (offset 0x314).
  • Clarified in topic Clocking and Reset Structure that the transceiver reference clock (tx_pll_refclk) and the system clock (sys_clk) inputs must be generated from the same clock source.
  • Corrected the descriptions of Port 0 Packet Capture 1-3 CSRs.
  • Clarified in Appendix Differences Between RapidIO II MegaCore Function v12.1 and RapidIO MegaCore Function v12.1:
    • In the RapidIO II IP core, you cannot independently select whether or not to support port-write transactions. If you include a Maintenance module in your design, your IP core supports port-write transactions.
    • In the RapidIO II IP core (in contrast to the RapidIO IP core) on the Avalon® -ST passthrough interface in the RX direction only, the sourceID and destinationID fields in gen_rx_hd_data are 16 bits wide even if the device ID width for the IP core variation is 8 bits. However, in the TX direction, as in the RapidIO IP core, the sourceID and destinationID field width depends on the device ID width.
    • Since v13.0, RapidIO IP core has 2x variations, which has same Avalon® -MM I/O Logical layer data bus width as the 4x variations.
    • In Sending Link-Request Reset-Device on Fatal Errors parameter entry, added information for full comparison.
  • Modified the description of Port 0 Attributes Capture CSR (offset 0x348).
  • Corrected Chapter Testbench to state that the Intel-provided testbench does not generate packets with ftype 9.
  • Corrected number of TX Maintenance windows indicated in Chapter Software Interface.
  • Corrected descriptions of IDLE2 Received bit in LP-Serial Lane n Status 1 CSR and CMD changed bit in LP-Serial Lane n Status 3 CSR.
  • Corrected the width of the values of the destinationID and sourceID fields of the gen_tx_data bus in the Avalon® -ST pass-through interface usage example User Sending Read Request and Receiving Read Response to match field width.
  • Corrected the default value for ExtendedFeaturesPtr field in Assembly Information CAR (offset 0x0C).
  • Corrected the default value for LP-Serial Lane n Status 4 register bit [28] (Scrambling/Descrambling enabled).
  • Corrected access mode for LP-Serial Lane n Status 4 register bit [30] (Impl defined).
  • Corrected bit range for Connected port transmit emphasis Tap (-1) status field in LP-Serial Lane n Status 1 register.
  • Corrected offset for Port 0 Link Maintenance Response register in the Extended Features and Implementation-Defined Registers Memory Map.
  • Corrected description of RESPONSE_VALID bit of Port 0 Link Maintenance Response CSR (offset 0x140).
  • Corrected Maintenance Avalon® -MM master signal names.
  • Changed erroneous mention of link-request reset-device control symbol to link-request input-status control symbol.
November 2012 Initial release.
Level Two Title