3.2. RTL Parameters

H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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Date 5/03/2024

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3.2. RTL Parameters

The H-Tile Hard IP for Ethernet IP core provides parameters in the generated RTL that you can modify for your IP core instance. Generating an IP core variation from the parameter editor creates an RTL module. Your design might instantiate multiple instances of this module. You can specify RTL parameter values for each instance. Each RTL parameter determines the initial and reset value of one or more register fields in the IP core.

RTL parameters allow you to customize your IP core instance to vary from the defaults you selected for your IP core variation and from other instances of the same IP core variation. This capability allows you to fine-tune your design without regenerating and without reading and writing registers following power-up. In addition, you can specify parameter values that should not be identical for multiple instances. For example, you can specify a different TX source address for each instance, without having to write to the relevant registers.

To access the RTL parameters, refer to the IP configuration and test files. The simulation-based RTL parameters are located in <your_project_directory>\<your_IP_name>\sim\<your_IP_name>.v The synthesis-based RTL parameters are located in <your_project_directory>\<your_IP_name>\synth\<your_IP_name>.v.

Table 10. H-Tile Hard IP for Ethernet RTL Parameters
Parameter	Parameter Description
Parameters Available for all IP Core Variations
`sim_mode`	Specifies whether the IP core is in simulation mode, in which alignment marker periods are shortened to decrease the time to RX PCS alignment. Value `enable` (default value): The IP core implements shorter alignment marker periods to accelerate RX PCS alignment in simulation. The simulation link partner must have the same alignment marker periods. This mode is intended for simulation only. Value `disable`: The IP core MAC implements standard alignment marker periods as specified in the IEEE Standard 802.3–2015. The value of this parameter determines the initial and reset values of these register fields: `am_interval[13:0]` field (bits [13:0]) of the `RXPCS_CONF` register at 0ffset 0x360. `am_period[15:0]` field (bits [31:16]) of the `TXMAC_EHIP_CFG` register at 0ffset 0x40B.
Parameters Available for MAC+PCS IP Core Variations Only
`rx_pause_daddr`	Sets the destination address for PAUSE and PFC frames. The RX MAC uses this address to filter whether incoming PAUSE and PFC frames apply to the current IP core. Default value is 0x01_80_C2_00_00_01, the Ethernet standard multicast address for PAUSE and PFC. Range is 0 through 2⁴⁸–1. Value can be a unicast or multicast address. The RX MAC processes PAUSE and PFC frames only if their destination address matches this address (actually, the address in the `RX_PAUSE_DADDR` registers). The value of this parameter determines the initial and reset values of the `RX_PAUSE_DADDR` registers at offsets 0x707 and 0x708.
`source_address_insertion`	Selects whether the IP core supports overwriting the source address in an outgoing packet it receives on the TX MAC interface, with the value in the `TXMAC_SADDR` registers at offsets 0x40C and 0x40D. The default value is the value of the parameter editor Use source address insertion parameter. Value `enable`: If `i_tx_skip_crc` has the value of 0, in packets the IP core receives on the TX MAC client interface, the TX MAC overwrites the source address field with the value in the `TXMAC_SADDR` registers at offsets 0x40C and 0x40D. Note: The IP core does not overwrite the source address in Ethernet PAUSE and PFC packets it generates on the Ethernet link in response to assertion of the `i_tx_pause` signal or an `i_tx_pfc[n]` signal on the TX MAC client interface. Value `disable`: The TX MAC does not overwrite the source address field in packets it receives on the TX MAC client interface. The value of this parameter determines the initial and reset values of the `en_saddr_insert` field (bit [3]) of the `TXMAC_CONTROL` register at 0ffset 0x40A.
`tx_pause_daddr`	Sets the destination address that the TX MAC inserts in PAUSE and PFC frames that the IP core transmits on the Ethernet link in response to assertion of the `i_tx_pause` signal or an `i_tx_pfc[n]` signal on the TX MAC client interface. Default value is 0x01_80_C2_00_00_01, the Ethernet standard multicast address for PAUSE and PFC. Range is 0 through 2⁴⁸–1. Value can be a unicast or multicast address. The value of this parameter determines the initial and reset values of the `TX_PFC_DADDR` registers at offsets 0x60D and 0x60E.
`tx_pause_saddr`	Sets the source address that the TX MAC inserts in PAUSE and PFC frames that the IP core transmits on the Ethernet link in response to assertion of the `i_tx_pause` signal or an `i_tx_pfc[n]` signal on the TX MAC client interface. Default value is the value of the RTL parameter `txmac_saddr`, which is the initial source address the IP core inserts in all TX packets written to the TX MAC client interface when source MAC address insertion is enabled. Range is 0 through 2⁴⁸–1. Value should be a unicast address. The value of this parameter determines the initial and reset values of the `TX_PFC_SADDR` registers at offsets 0x60F and 0x610.
`txmac_saddr`	Sets the source address that the TX MAC inserts in packets written to the TX MAC client interface when source MAC address insertion is enabled. Default value is the value you specify for the parameter editor TX MAC source address parameter. Range is 0 through 2⁴⁸–1. The Intel® FPGA team recommends you program each IP core instance with a unique unicast MAC address. The value of this parameter determines the initial and reset values of the `TXMAC_SADDR` registers at offsets 0x40C and 0x40D.

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H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

3.2. RTL Parameters