6.8. Transceiver Reconfiguration Signals

H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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Date 5/03/2024

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6.8. Transceiver Reconfiguration Signals

You access the transceiver dynamic reconfiguration registers using the transceiver reconfiguration interface. This Avalon-MM interface provides access to the transceiver registers.

The Avalon-MM interface implements a standard memory-mapped protocol. You can connect an Avalon master to this bus to access the registers of the embedded Stratix® 10 Native PHY IP cores.

Table 21. Transceiver Reconfiguration Interface Ports to Native PHY Reconfiguration InterfacesThe signals in this interface are clocked by the `i_reconfig_clk` clock and reset by the `i_reconfig_reset` signal. Each bus is a concatenation of the signals for the individual transceiver channels. IP core has four individual transceiver channels.
Port Name	Description
`i_xcvr_reconfig_write[3:0]`	Write request signal. Signal is active high. To request to write to any of the transceiver reconfiguration registers of the transceiver channel that is configured for lane `n`, assert `i_xcvr_reconfig_write[n]`.
`i_xcvr_reconfig_read[3:0]`	Read request signal. Signal is active high. To request to read from any of the transceiver reconfiguration registers of the transceiver channel that is configured for lane `n`, assert `i_xcvr_reconfig_read[n]`.
`i_xcvr_reconfig_address[43:0]`	Address bus. Drive the register address for the transceiver reconfiguration register to which you wish to write or from which you wish to read, on the corresponding 11 bits of `i_xcvr_reconfig_address`. For example, if you wish to read the value in the transceiver reconfiguration register at offset 0x4E0 for lane 1, drive the value of 0x4E0 on `i_xcvr_reconfig_address[21:11]` while you assert `i_xcvr_reconfig_read[1]`.
`i_xcvr_reconfig_writedata[63:0]`	Write data bus. `i_xcvr reconfig_address[(11(n+1)-1:11n]` specifies the write address for the write data on `i_xcvr_reconfig_writedata[16(n+1)-1:16n]`. For example, to write to the transceiver reconfiguration register address at offset 0x4E0 for lane 1, drive the register address on `i_xcvr reconfig_address[21:11]`, assert `i_xcvr_reconfig_read[1]`, and write the data to `i_xcvr_reconfig_writedata[31:16]`.
`o_xcvr_reconfig_readdata[63:0]`	Read data bus. `i_xcvr reconfig_address[(11(n+1)-1:11n]` specifies the read address for the read data on `o_xcvr_reconfig_readdata[16(n+1)-1:16n]`. For example, to read from the transceiver reconfiguration register address at offset 0x4E0 for lane 1, drive the register address on `i_xcvr reconfig_address[21:11]`, assert `i_xcvr_reconfig_write[1]`, and after `o_xcvr_reconfig_waitrequest[1]` is deasserted, read the data on `o_xcvr_reconfig_readdata[31:16]`. Note that the `o_xcvr_reconfig_readdata` bit range for a lane is valid only after the corresponding bit of `o_xcvr_reconfig_waitrequest` is deasserted.
`o_xcvr_reconfig_waitrequest[3:0]`	Indicates the Avalon® memory-mapped interface is busy. Keep each `i_xcvr_reconfig_write` or `i_xcvr_reconfig_read` bit asserted until the corresponding `o_xcvr_reconfig_waitrequest` bit is deasserted.

Figure 31. Writing to Transceiver Reconfiguration CSRs through Transceiver Avalon Memory-Mapped (MM) InterfaceRequirements when performing a write to transceiver reconfiguration CSRs:

The write request must hold high until o_xcvr_reconfig_waitrequest is de-asserted if the write begins while o_xcvr_reconfig_waitrequest is high.
Wait for o_xcvr_reconfig_waitrequest to go high after asserting a write command. Hold the write command until o_xcvr_reconfig_waitrequest goes low again.
Reads and writes cannot be performed simultaneously.
When multiple CSRs have the same address, you may need to perform a Read-Modify-Write to change the desired CSR without changing the value of the CSRs in the same address.

Figure 32. Reading from Transceiver Reconfiguration CSRs through Transceiver Avalon Memory-Mapped (MM) InterfaceRequirements when performing a read to transceiver reconfiguration CSRs:

The read request must hold high until o_xcvr_reconfig_waitrequest is de-asserted if the read begins while o_xcvr_reconfig_waitrequest is high.
Wait for o_xcvr_reconfig_waitrequest to go high after asserting a read command. Hold the read command until o_xcvr_reconfig_waitrequest goes low again.
Reads and writes cannot be performed simultaneously.

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H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

6.8. Transceiver Reconfiguration Signals