H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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ID 683430
Date 5/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the H-Tile Hard IP for Ethernet IP Core 2. Getting Started 3. H-Tile Hard IP for Ethernet Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Ethernet Toolkit Overview 8. H-Tile Hard IP for Ethernet IP User Guide Archives 9. Document Revision History for the H-Tile Hard IP for Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices A. Advanced RTL Parameters B. Ethernet Reconfiguration and Status Register Descriptions
1. About the H-Tile Hard IP for Ethernet IP Core x
1.1. IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. H-Tile Hard IP for Ethernet IP Core Device Family Support 1.2.2. H-Tile Hard IP for Ethernet IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design 2.5. IP Core Testbenches 2.6. Compiling the Full Design and Programming the FPGA
2.4. Integrating Your IP Core in Your Design x
2.4.1. Channel Placement 2.4.2. Pin Assignments 2.4.3. Adding the Transceiver PLLs 2.4.4. Clock Requirements 2.4.5. Placement Settings for the H-Tile Hard IP for Ethernet IP Core
2.4.4. Clock Requirements x
2.4.4.1. Clock Connection Requirements
3. H-Tile Hard IP for Ethernet Parameters x
3.1. Parameter Editor Parameters 3.2. RTL Parameters
4. Functional Description x
4.1. High Level System Overview 4.2. H-Tile Hard IP for Ethernet IP Core MAC Interface 4.3. H-Tile Hard IP for Ethernet IP PCS Only/PCS66 Interface 4.4. Auto-Negotiation and Link Training
4.2. H-Tile Hard IP for Ethernet IP Core MAC Interface x
4.2.1. H-Tile Hard IP for Ethernet IP Core TX Datapath 4.2.2. H-Tile Hard IP for Ethernet IP Core RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Pause Control and Generation Interface 4.2.5. Pause Control Frame Filtering 4.2.6. Link Fault Signaling 4.2.7. Statistics Counters Interface 4.2.8. Order of Ethernet Transmission
4.2.1. H-Tile Hard IP for Ethernet IP Core TX Datapath x
4.2.1.1. Preamble, Start, and SFD Insertion 4.2.1.2. Length/Type Field Processing 4.2.1.3. Frame Padding 4.2.1.4. Frame Check Sequence (CRC-32) Insertion 4.2.1.5. Inter-Packet Gap Generation and Insertion
4.2.2. H-Tile Hard IP for Ethernet IP Core RX Datapath x
4.2.2.1. H-Tile Hard IP for Ethernet IP Core RX Filtering 4.2.2.2. H-Tile Hard IP for Ethernet IP Core Preamble Processing 4.2.2.3. IP Core Strict SFD Checking 4.2.2.4. RX FCS Checking 4.2.2.5. RX Malformed Packet Handling 4.2.2.6. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.7. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.8. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission
4.2.7. Statistics Counters Interface x
4.2.7.1. Statistic Counters Rollover Limitations
4.3. H-Tile Hard IP for Ethernet IP PCS Only/PCS66 Interface x
4.3.1. TX PCS and RX PCS Datapath
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. TX PCS Interface to User Logic 6.4. RX PCS Interface to User Logic 6.5. FlexE and OTN Mode TX Interface 6.6. FlexE and OTN Mode RX Interface 6.7. Ethernet Link and Transceiver Signals 6.8. Transceiver Reconfiguration Signals 6.9. Ethernet Reconfiguration Interface 6.10. Miscellaneous Status and Debug Signals 6.11. Reset Signals 6.12. Clocks
6.8. Transceiver Reconfiguration Signals x
6.8.1. Disabling Background Calibration
7. Ethernet Toolkit Overview x
7.1. Features
B. Ethernet Reconfiguration and Status Register Descriptions x
B.1. Auto-Negotiation and Link Training Registers B.2. PHY Registers B.3. TX MAC Registers B.4. RX MAC Registers B.5. Pause and Priority- Based Flow Control Registers B.6. TX Statistics Counter Registers B.7. RX Statistics Counter Registers
B.1. Auto-Negotiation and Link Training Registers x
B.1.1. ANLT Sequencer Config B.1.2. ANLT Sequencer Status B.1.3. Auto-Negotiation Config Register 1 B.1.4. Auto-Negotiation Config Register 2 B.1.5. Auto-Negotiation Status Register B.1.6. Auto Negotiation Config Register 3 B.1.7. Auto-Negotiation Config Register 4 B.1.8. Auto-Negotiation Config Register 5 B.1.9. Auto-Negotiation Config Register 6 B.1.10. Auto-Negotiation Status Register 1 B.1.11. Auto-Negotiation Status Register 2 B.1.12. Auto-Negotiation Status Register 3 B.1.13. Auto-Negotiation Status Register 4 B.1.14. Auto-Negotiation Status Register 5 B.1.15. Consortium Next Page Override B.1.16. Consortium Next Page Link Partner Status B.1.17. Link Training Config Register 1 B.1.18. Link Training Config Register 2 B.1.19. Link Training Status Register 1 B.1.20. Link Training Config Register for Lane 0 B.1.21. Link Training Frame Contents for Lane 0 B.1.22. Local Transceiver TX EQ 1 Settings for Lane 0 B.1.23. Local Transceiver TX EQ 2 Settings for Lane 0 B.1.24. Local Link Training Parameters B.1.25. Link Training Config Register for Lane 1 B.1.26. Link Training Frame Contents for Lane 1 B.1.27. Local Transceiver TX EQ 1 Settings for Lane 1 B.1.28. Local Transceiver TX EQ 2 Settings for Lane 1 B.1.29. Link Training Config Register for Lane 2 B.1.30. Link Training Frame Contents for Lane 2 B.1.31. Local Transceiver TX EQ 1 Settings for Lane 2 B.1.32. Local Transceiver TX EQ 2 Settings for Lane 2 B.1.33. Link Training Config Register for Lane 3 B.1.34. Link Training Frame Contents for Lane 3 B.1.35. Local Transceiver TX EQ 1 Settings for Lane 3 B.1.36. Local Transceiver TX EQ 2 Settings for Lane 3
B.2. PHY Registers x
B.2.1. PHY Module Revision ID B.2.2. PHY Scratch Register B.2.3. PHY Configuration B.2.4. PMA Serial Loopback B.2.5. TX PLL Locked B.2.6. RX CDR PLL Locked B.2.7. TX Datapath Ready B.2.8. Frame Errors Detected B.2.9. Clear Frame Errors B.2.10. Reset Registers B.2.11. RX PCS Status for AN/LT B.2.12. PCS Error Injection B.2.13. Alignment Marker Lock B.2.14. BER Count B.2.15. PCS Virtual Lane 0 B.2.16. PCS Virtual Lane 1 B.2.17. PCS Virtual Lane 2 B.2.18. PCS Virtual Lane 3 B.2.19. Recovered Clock Frequency in KHz B.2.20. TX Clock Frequency in KHz
B.3. TX MAC Registers x
B.3.1. TX MAC Module Revision ID B.3.2. TX MAC Scratch Register B.3.3. Reserved B.3.4. Link Fault Configuration B.3.5. IPG Words to remove per Alignment Marker Period B.3.6. Maximum TX Frame Size B.3.7. TX MAC Configuration B.3.8. EHIP TX MAC Feature Configuration B.3.9. TX MAC Source Address Lower Bytes B.3.10. TX MAC Source Address Higher Bytes
B.4. RX MAC Registers x
B.4.1. RX MAC Module Revision ID B.4.2. RX MAC Scratch Register B.4.3. Reserved B.4.4. Maximum RX Frame Size B.4.5. RX CRC Forwarding B.4.6. Link Fault Status B.4.7. RX MAC Configuration B.4.8. EHIP RX MAC Feature Configuration
B.5. Pause and Priority- Based Flow Control Registers x
B.5.1. TXSFC Module Revision ID B.5.2. TX SFC Scratch Register B.5.3. Reserved B.5.4. Enable TX Pause Ports B.5.5. TX Pause Request B.5.6. Enable Automatic TX Pause Retransmission B.5.7. Retransmit Holdoff Quanta B.5.8. Retransmit Pause Quanta B.5.9. Enable TX XOFF B.5.10. Enable Uniform Holdoff B.5.11. Set Uniform Holdoff B.5.12. Lower 4 bytes of the Destination address for Flow Control B.5.13. Higher 2 bytes of the Destination address for Flow Control B.5.14. Lower 4 bytes of the Source address for Flow Control frames B.5.15. Higher 2 bytes of the Source address for Flow Control frames B.5.16. TX Flow Control Feature Configuration B.5.17. Pause Quanta 0 B.5.18. Pause Quanta 1 B.5.19. Pause Quanta 2 B.5.20. Pause Quanta 3 B.5.21. Pause Quanta 4 B.5.22. Pause Quanta 5 B.5.23. Pause Quanta 6 B.5.24. Pause Quanta 7 B.5.25. PFC Holdoff Quanta 0 B.5.26. PFC Holdoff Quanta 1 B.5.27. PFC Holdoff Quanta 2 B.5.28. PFC Holdoff Quanta 3 B.5.29. PFC Holdoff Quanta 4 B.5.30. PFC Holdoff Quanta 5 B.5.31. PFC Holdoff Quanta 6 B.5.32. PFC Holdoff Quanta 7 B.5.33. RXSFC Module Revision ID B.5.34. RXSFC Scratch Register B.5.35. Reserved B.5.36. Enable RX Pause Frame Processing B.5.37. Forward Flow Control Frames B.5.38. Lower 4 bytes of the Destination address for RX Pause Frames B.5.39. Higher 2 bytes of the Destination address for RX Pause Frames
B.6. TX Statistics Counter Registers x
B.6.1. TX Frames less than 64 bytes with CRC error (lower 32 bits) B.6.2. TX Frames less than 64 bytes with CRC error (upper 32 bits) B.6.3. Oversized TX frames with CRC error (lower 32 bits) B.6.4. Oversized TX frames with CRC error (upper 32 bits) B.6.5. TX Frames of any size with a CRC error (lower 32 bits) B.6.6. TX Frames of any size with a CRC error (upper 32 bits) B.6.7. TX Frames of any size with a CRC error on OK packet (lower 32 bits) B.6.8. TX Frames of any size with a CRC error on OK packet (upper 32 bits) B.6.9. Multicast TX data frames with CRC error (lower 32 bits) B.6.10. Multicast TX data frames with CRC error (upper 32 bits) B.6.11. Broadcast TX data frames with CRC error (lower 32 bits) B.6.12. Broadcast TX data frames with CRC error (upper 32 bits) B.6.13. Unicast TX data frames with CRC error (lower 32 bits) B.6.14. Unicast TX data frames with CRC error (upper 32 bits) B.6.15. Multicast TX control frames with CRC error (lower 32 bits) B.6.16. Multicast TX control frames with CRC error (upper 32 bits) B.6.17. Broadcast TX control frames with CRC error (lower 32 bits) B.6.18. Broadcast TX control frames with CRC error (upper 32 bits) B.6.19. Unicast TX control frames with CRC error (lower 32 bits) B.6.20. Unicast TX control frames with CRC error (upper 32 bits) B.6.21. TX Pause frame with CRC error (lower 32 bits) B.6.22. TX Pause frame with CRC error (upper 32 bits) B.6.23. 64 byte TX frames (lower 32 bits) B.6.24. 64 byte TX frames (upper 32 bits) B.6.25. 65 to 127 byte TX frames (lower 32 bits) B.6.26. 65 to 127 byte TX frames (upper 32 bits) B.6.27. 128 to 257 byte TX frames (lower 32 bits) B.6.28. 128 to 257 byte TX frames (upper 32 bits) B.6.29. 256 to 511 byte TX frames (lower 32 bits) B.6.30. 256 to 511 byte TX frames (upper 32 bits) B.6.31. 512 to 1023 byte TX frames (lower 32 bits) B.6.32. 512 to 1023 byte TX frames (upper 32 bits) B.6.33. 1024 to 1518 byte TX frames (lower 32 bits) B.6.34. 1024 to 1518 byte TX frames (upper 32 bits) B.6.35. 1519 to max size TX frames (lower 32 bits) B.6.36. 1519 to max size TX frames (upper 32 bits) B.6.37. Oversize TX frames (lower 32 bits) B.6.38. Oversize TX frames (upper 32 bits) B.6.39. Multicast TX data frames without error (lower 32 bits) B.6.40. Multicast TX data frames without error (upper 32 bits) B.6.41. Broadcast TX data frames without error (lower 32 bits) B.6.42. Broadcast TX data frames without error (upper 32 bits) B.6.43. Unicast TX data frames without error (lower 32 bits) B.6.44. Unicast TX data frames without error (upper 32 bits) B.6.45. Multicast TX control frames without error (lower 32 bits) B.6.46. Multicast TX control frames without error (upper 32 bits) B.6.47. Broadcast TX control frames without error (lower 32 bits) B.6.48. Broadcast TX control frames without error (upper 32 bits) B.6.49. Unicast TX control frames without error (lower 32 bits) B.6.50. Unicast TX control frames without error (upper 32 bits) B.6.51. TX Pause frames without error (lower 32 bits) B.6.52. TX Pause frames without error (upper 32 bits) B.6.53. TX Frames with less than 64 bytes and a CRC error (lower 32 bits) B.6.54. TX Frames with less than 64 bytes and a CRC error (upper 32 bits) B.6.55. Number of TX frame starts (lower 32 bits) B.6.56. Number of TX frame starts (upper 32 bits) B.6.57. Number of TX length errors (lower 32 bits) B.6.58. Number of TX length errors (upper 32 bits) B.6.59. TX PFC frame with CRC error (lower 32 bits) B.6.60. TX PFC frame with CRC error (upper 32 bits) B.6.61. TX PFC frames without error (lower 32 bits) B.6.62. TX PFC frames without error (upper 32 bits) B.6.63. TXSTAT Module Revision ID B.6.64. TXSTAT Scratch Register B.6.65. Reserved B.6.66. Configure TX Statistics Counters B.6.67. TX Statistics Counter Status B.6.68. TX Payload bytes with no errors (lower 32 bits) B.6.69. TX Payload bytes with no errors (upper 32 bits) B.6.70. TX Frame bytes with no errors (lower 32 bits) B.6.71. TX Frame bytes with no errors (upper 32 bits) B.6.72. TX Malformed frames (lower 32 bits) B.6.73. TX Malformed frames (upper 32 bits) B.6.74. TX Packets that were dropped due to error (lower 32 bits) B.6.75. TX Packets that were dropped due to error (upper 32 bits) B.6.76. TX Frames with bad length/type field (lower 32 bits) B.6.77. TX Frames with bad length/type field (upper 32 bits)
B.7. RX Statistics Counter Registers x
B.7.1. RX Frames less than 64 bytes with CRC error (lower 32 bits) B.7.2. RX Frames less than 64 bytes with CRC error (upper 32 bits) B.7.3. Oversized RX frames with CRC error (lower 32 bits) B.7.4. Oversized RX frames with CRC error (upper 32 bits) B.7.5. RX Frames of any size with a CRC error (lower 32 bits) B.7.6. RX Frames of any size with a CRC error (upper 32 bits) B.7.7. RX Frames of any size with a CRC error on OK packet (lower 32 bits) B.7.8. RX Frames of any size with a CRC error on OK packet (upper 32 bits) B.7.9. Multicast RX data frames with CRC error (lower 32 bits) B.7.10. Multicast RX data frames with CRC error (upper 32 bits) B.7.11. Broadcast RX data frames with CRC error (lower 32 bits) B.7.12. Broadcast RX data frames with CRC error (upper 32 bits) B.7.13. Unicast RX data frames with CRC error (lower 32 bits) B.7.14. Unicast RX data frames with CRC error (upper 32 bits) B.7.15. Multicast RX control frames with CRC error (lower 32 bits) B.7.16. Multicast RX control frames with CRC error (upper 32 bits) B.7.17. Broadcast RX control frames with CRC error (lower 32 bits) B.7.18. Broadcast RX control frames with CRC error (upper 32 bits) B.7.19. Unicast RX control frames with CRC error (lower 32 bits) B.7.20. Unicast RX control frames with CRC error (upper 32 bits) B.7.21. RX Pause frame with CRC error (lower 32 bits) B.7.22. RX Pause frame with CRC error (upper 32 bits) B.7.23. 64 byte RX frames (lower 32 bits) B.7.24. 64 byte RX frames (upper 32 bits) B.7.25. 65 to 127 byte RX frames (lower 32 bits) B.7.26. 65 to 127 byte RX frames (upper 32 bits) B.7.27. 128 to 257 byte RX frames (lower 32 bits) B.7.28. 128 to 257 byte RX frames (upper 32 bits) B.7.29. 256 to 511 byte RX frames (lower 32 bits) B.7.30. 256 to 511 byte RX frames (upper 32 bits) B.7.31. 512 to 1023 byte RX frames (lower 32 bits) B.7.32. 512 to 1023 byte RX frames (upper 32 bits) B.7.33. 1024 to 1518 byte RX frames (lower 32 bits) B.7.34. 1024 to 1518 byte RX frames (upper 32 bits) B.7.35. 1519 to max size RX frames (lower 32 bits) B.7.36. 1519 to max size RX frames (upper 32 bits) B.7.37. Oversize RX frames (lower 32 bits) B.7.38. Oversize RX frames (upper 32 bits) B.7.39. Multicast RX data frames without error (lower 32 bits) B.7.40. Multicast RX data frames without error (upper 32 bits) B.7.41. Broadcast RX data frames without error (lower 32 bits) B.7.42. Broadcast RX data frames without error (upper 32 bits) B.7.43. Unicast RX data frames without error (lower 32 bits) B.7.44. Unicast RX data frames without error (upper 32 bits) B.7.45. Multicast RX control frames without error (lower 32 bits) B.7.46. Multicast RX control frames without error (upper 32 bits) B.7.47. Broadcast RX control frames without error (lower 32 bits) B.7.48. Broadcast RX control frames without error (upper 32 bits) B.7.49. Unicast RX control frames without error (lower 32 bits) B.7.50. Unicast RX control frames without error (upper 32 bits) B.7.51. RX Pause frames without error (lower 32 bits) B.7.52. RX Pause frames without error (upper 32 bits) B.7.53. RX Frames with less than 64 bytes and a CRC error (lower 32 bits) B.7.54. RX Frames with less than 64 bytes and a CRC error (upper 32 bits) B.7.55. Number of RX frame starts (lower 32 bits) B.7.56. Number of RX frame starts (upper 32 bits) B.7.57. Number of RX length errors (lower 32 bits) B.7.58. Number of RX length errors (upper 32 bits) B.7.59. RX PFC frame with CRC error (lower 32 bits) B.7.60. RX PFC frame with CRC error (upper 32 bits) B.7.61. RX PFC frames without error (lower 32 bits) B.7.62. RX PFC frames without error (upper 32 bits) B.7.63. RXSTAT Module Revision ID B.7.64. RXSTAT Scratch Register B.7.65. Reserved B.7.66. Reserved B.7.67. Reserved B.7.68. Configure RX Statistics Counters B.7.69. RX Statistics Counter Status B.7.70. RX Payload bytes with no errors (lower 32 bits) B.7.71. RX Payload bytes with no errors (upper 32 bits) B.7.72. RX Frame bytes with no errors (lower 32 bits) B.7.73. RX Frame bytes with no errors (upper 32 bits) B.7.74. RX Malformed frames (lower 32 bits) B.7.75. RX Malformed frames (upper 32 bits) B.7.76. RX Packets that were dropped due to error (lower 32 bits) B.7.77. RX Packets that were dropped due to error (upper 32 bits) B.7.78. RX Frames with bad length/type field (lower 32 bits) B.7.79. RX Frames with bad length/type field (upper 32 bits)
1. About the H-Tile Hard IP for Ethernet IP Core
2. Getting Started
3. H-Tile Hard IP for Ethernet Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Ethernet Toolkit Overview
8. H-Tile Hard IP for Ethernet IP User Guide Archives
9. Document Revision History for the H-Tile Hard IP for Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices
A. Advanced RTL Parameters
B. Ethernet Reconfiguration and Status Register Descriptions

A. Advanced RTL Parameters

The H-Tile Hard IP for Ethernet IP core provides advanced parameters in the generated RTL that you can modify for your IP core instance. In most cases you should leave these parameters at their default values.

RTL parameters allow you to customize your IP core instance to vary from the defaults you selected for your IP core variation and from other instances of the same IP core variation. This capability allows you to fine-tune your design without regenerating and without reading and writing registers following power-up. In addition, you can specify parameter values that should not be identical for multiple instances. For example, you can specify a different TX source address for each instance, without having to write to the relevant registers.

The most useful RTL parameters are listed in the RTL Parameters section. The RTL parameters in this appendix are provided for advanced applications. In most cases these parameters are not useful, either because all IP core instances in the same design usually have the same value and the parameter editor parameter suffices to specify the value, or because the Intel® PSG team recommends that you use the default value.

Table 27.   H-Tile Hard IP for Ethernet IP RTL Parameters

Parameter

Parameter Description

Parameters Available for all IP Core Variations
hi_ber_monitor Enables the RX PCS hi-BER monitor.
  • Value enable (default value): Ethernet standard compliant setting. The IP core hi-BER monitor is turned on. The RX PCS counts the number of RX frame header errors according to Figure 82-15 in the IEEE Standard 802.3–2015, using the xus_timer_window and ber_invalid_count values appropriate for the IP core data rate. When the IP core detects a hi_ber condition, it sets the value of the o_hi_ber signal to the value of 1.
  • Value disable: The hi-BER monitor is turned off.

The value of this parameter determines the initial and reset values of the use_hi_ber_monitor field (bit [20]) of the RXPCS_CONF register at 0ffset 0x360.

rx_pcs_max_skew Specifies the maximum RX PCS skew the IP core allows.
  • Value range is 1 through 47 (decimal).
  • Default value is 47 decimal.
  • You can modify this value for testing.

The value of this parameter determines the initial and reset values of the rc_pcs_max_skew[5:0] field (bits [19:14]]) of the RXPCS_CONF register at 0ffset 0x360.

Parameters Available for MAC+PCS IP Core Variations Only
enforce_max_frame_size Specifies whether the IP core is able to receive an oversized packet or truncates these packets.
  • Default value is the value you specified for the Enforce maximum frame size parameter.
  • Value disable: For RX frames that exceed the value of the RTL parameter rx_max_frame_size, the IP core increments the RX oversized packets counter at offsets 0x924 and 0x925 and sets bit [3] (oversized) of the o_rx_error bus on the RX client interface at the appropriate time.
  • Value enable: For RX frames that exceed the value of the RTL parameter rx_max_frame_size, the IP core truncates the packet to the maximum RX frame size, increments the RX oversized packets counter at offsets 0x924 and 0x925, increments the appropriate RX FCS error packet counters, and sets bits [3] (oversized) and [1] (CRC error) of the o_rx_error bus on the RX client interface at the appropriate time.

The value of this parameter determines the initial and reset values of the enforce_max_rx field (bit [7]) of the RXMAC_CONTROL register at 0ffset 0x50A.

flow_control

Sets the flow control mode for the TX and RX MAC.

  • Value none (default if the parameter editor Stop TX traffic when link partner sends pause parameter has the value of Disable Flow Control): The IP core does not implement flow control.
  • Value sfc: The IP core implements strictly compliant Ethernet standard flow control. Both the i_tx_pause and o_rx_pause ports are functioning, and the TX MAC stops traffic if the IP core receives a PAUSE XOFF frame on the Ethernet link.
  • Value sfc_no_xoff: Both the i_tx_pause and o_rx_pause ports are functioning, but the TX MAC does not stop traffic if the IP core receives a PAUSE XOFF frame on the Ethernet link.
  • Value pfc: Both the i_tx_pfc and o_rx_pfc ports are functioning, and the TX MAC stops traffic if the IP core receives a PAUSE XOFF frame on the Ethernet link.
  • Value pfc_no_xoff: The IP core implements strictly compliant Ethernet priority flow control. Both the i_tx_pfc and o_rx_pfc ports are functioning, but the TX MAC does not stop traffic if the IP core receives a PAUSE XOFF frame on the Ethernet link.
  • Value both (default if the parameter editor Stop TX traffic when link partner sends pause parameter has the value of Yes): All of the i_tx_pause, o_rx_pause, i_tx_pfc, and o_rx_pfc ports are functioning, and the TX MAC stops traffic if the IP core receives a PAUSE XOFF frame on the Ethernet link.
  • Value both_no_xoff (default if the parameter editor Stop TX traffic when link partner sends pause parameter has the value of No): All of the i_tx_pause, o_rx_pause, i_tx_pfc, and o_rx_pfc ports are functioning, but the TX MAC does not stop traffic if the IP core receives a PAUSE XOFF frame on the Ethernet link.

The value of this parameter determines the initial and reset values of these register fields:

  • en_pfc_port[8:0] field (bits [8:0]) of the TX_PAUSE_EN register at 0ffset 0x605.
  • en_xoff_qnum_sel[2:0] field (bits [2:0]) of the TX_XOF_EN_TX_PAUSE_QNUMBER register at 0ffset 0x60A.
  • en_sfc field (bit [0]) of the TXSFC_EHIP_CFG register at 0ffset 0x611.
  • en_pfc field (bit [1]) of the TXSFC_EHIP_CFG register at 0ffset 0x611.
  • en_rx_pause[7:0] field (bits [7:0]) of the RX_PAUSE_ENABLE register at 0ffset 0x705.
  • en_sfc field (bit [0]) of the RXSFC_EHIP_CFG register at 0ffset 0x709.
  • en_pfc field (bit [1]) of the RXSFC_EHIP_CFG register at 0ffset 0x709.
flow_control_holdoff_mode Sets the holdoff timer source for the TX PAUSE and TX PFC queues.
  • Value per_queue (default value): The IP core regulates TX PAUSE (i_tx_pause) and each TX PFC queue (each i_tx_pfc[n]) with their own individual holdoff timers.
  • Value uniform: The IP core regulates TX PAUSE (i_tx_pause) and each TX PFC queue (each i_tx_pfc[n]) with the uniform holdoff timer. Each of these queues is regulated with the shorter of the uniform holdoff timer and its own individual holdoff timer. In priority flow control, if all queues have the same holdoff time, using this mode increases the chance that the IP core sends triggered XOFF frames for all PFC queues in the same Ethernet frame, increasing throughput.
  • Value no_holdoff: No holdoff timers. Not recommended.

The value of this parameter determines the initial and reset values of these register fields:

  • ldoff[8:0] field (bits [8:0]) of the RETRANSMIT_XOFF_HOLDOFF_EN register at 0ffset 0x607.
  • en_holdoff_all field (bit [0]) of the CFG_RETRANSMIT_HOLDOFF_EN register at 0ffset 0x60B.
forward_rx_pause_requests Selects whether the RX MAC forwards incoming PAUSE and PFC frames on the RX client interface or drops them after internal processing.
Note: If flow control is turned off, the IP core forwards all incoming PAUSE and PFC frames directly to the RX client interface and performs no internal processing.
  • Default value is the value you specified for the Forward RX pause requests parameter.
  • Value enable: The RX MAC forwards incoming PAUSE and PFC frames on the RX client interface.
  • Value disable: If flow control is turned on, the IP core does not forward incoming PAUSE and PFC frames on the RX client interface.

The value of this parameter determines the initial and reset values of the rx_pause_fwd field (bit [0]) of the RX_PAUSE_FWD register at 0ffset 0x706.

holdoff_quanta Sets the holdoff timer for the standard Ethernet flow control (PAUSE XOFF).
  • Default value is 32768.
  • Range is 1 through the largest number of quanta that ensures any PAUSE XOFF frame the IP core sends will arrive before the previous PAUSE XOFF frame expires.
  • The value of this parameter (actually, the register fields it affects) determines the frequency with which the TX MAC resends PAUSE XOFF frames while the corresponding PAUSE request is asserted.
  • This parameter counts quanta in 100GBASE-R4 variations.

The value of this parameter determines the initial and reset values of the holdoff_quanta[15:0] field (bits [15:0]) of the RETRANSMIT_XOFF_HOLDOFF_QUANTA register at 0ffset 0x608.

ipg_removed_per_am_period Specifies the number of inter-packet gaps the IP core removes per alignment marker period.
  • The default value of this parameter is 20 plus the value you specified for the parameter editor Additional IPG removed per AM period parameter. The correct value of the RTL parameter ipg_removed_per_am_period for standard 100-Gbps operation is 20.
  • Range is 1 through 216–1.
  • Each increment of 1 in the value of this parameter increases throughput by 3ppm.
  • To specify large throughput increases, use the tx_ipg_size RTL parameter instead of the ipg_removed_per_am_period RTL parameter.

The value of this parameter determines the initial and reset values of the ipg_col_rem[15:0] field (bits [15:0]) of the IPG_COL_REM register at 0ffset 0x406.

link_fault_mode Specifies the IP core TX MAC and RX MAC responses to link fault events.
  • Default value is the value you specified for the parameter editor Choose Link Fault generation option parameter.
  • Value lf_bidir: Complies with the Ethernet specification. Implements the state diagram in IEEE 802.3 Figure 81-11.
  • Value lf_unidir: Implements IEEE 802.3 Clause 66: in response to local faults, the IP core transmits Remote Fault ordered sets in interpacket gaps but does not respond to incoming Remote Fault ordered sets.
  • Value lf_off: Turns off TX MAC link fault responses. This option if provided for backward compatibility.

The value of this parameter determines the initial and reset values of these register fields:

  • en_lf field (bit [0]) of the LINK_FAULT_CONFIG register at 0ffset 0x405.
  • en_unidir field (bit [1]) of the LINK_FAULT_CONFIG register at 0ffset 0x405.
pause_quanta Specifies the number of quanta the TX MAC writes in PAUSE XOFF frames it transmits.
  • Default value is 65535.
  • Range is 1 through 65535 (216–1).
  • The Intel FPGA team recommends you maintain the maximum value for this parameter. The IP core can send a PAUSE XON packet at any time, to cancel the PAUSE XOFF request.

The value of this parameter determines the initial and reset values of the pause_quanta[15:0] field (bits [15:0]) of the TX_PAUSE_QUANTA register at 0ffset 0x609.

pfc_holdoff_quanta_0 Each parameter sets the holdoff timer for the priority flow control (PFC XOFF) for the corresponding queue. For each parameter:
  • Default value is 32768.
  • Range is 1 through the largest number of quanta that ensures any PFC XOFF frame the IP core sends will arrive before the previous PFC XOFF frame expires.
  • The value of this parameter (actually, the register field it affects) determines the frequency with which the TX MAC resends PFC XOFF frames while the corresponding PFC request is asserted.
  • This parameter counts quanta in 100GBASE-R4 variations.

The values of each of these parameters determines the initial and reset values of the following register for the corresponding queue:

  • holdoff_quanta[15:0] field (bits [15:0]) of the PFC_HOLDOFF_QUANTA_0 register at 0ffset 0x628
  • holdoff_quanta[15:0] field (bits [15:0]) of the PFC_HOLDOFF_QUANTA_1 register at 0ffset 0x629
  • holdoff_quanta[15:0] field (bits [15:0]) of the PFC_HOLDOFF_QUANTA_2 register at 0ffset 0x62A
  • holdoff_quanta[15:0] field (bits [15:0]) of the PFC_HOLDOFF_QUANTA_3 register at 0ffset 0x62B
  • holdoff_quanta[15:0] field (bits [15:0]) of the PFC_HOLDOFF_QUANTA_4 register at 0ffset 0x62C
  • holdoff_quanta[15:0] field (bits [15:0]) of the PFC_HOLDOFF_QUANTA_5 register at 0ffset 0x62D
  • holdoff_quanta[15:0] field (bits [15:0]) of the PFC_HOLDOFF_QUANTA_6 register at 0ffset 0x62E
  • holdoff_quanta[15:0] field (bits [15:0]) of the PFC_HOLDOFF_QUANTA_7 register at 0ffset 0x62F
pfc_holdoff_quanta_1
pfc_holdoff_quanta_2
pfc_holdoff_quanta_3
pfc_holdoff_quanta_4
pfc_holdoff_quanta_5
pfc_holdoff_quanta_6
pfc_holdoff_quanta_7
pfc_pause_quanta_0 Each parameter specifies the number of quanta the TX MAC writes in PFC XOFF frames it transmits for the corresponding queue. For each parameter:
  • Default value is 65535.
  • Range is 1 through 65535 (216–1).
  • The Intel FPGA team recommends you maintain the maximum value for this parameter. The IP core can send a PFC XON packet at any time, to cancel the PFC XOFF request.

The values of each of these parameters determines the initial and reset values of the following register for the corresponding queue:

  • pause_quanta[15:0] field (bits [15:0]) of the PFC_PAUSE_QUANTA_0 register at 0ffset 0x620
  • pause_quanta[15:0] field (bits [15:0]) of the PFC_PAUSE_QUANTA_1 register at 0ffset 0x621
  • pause_quanta[15:0] field (bits [15:0]) of the PFC_PAUSE_QUANTA_2 register at 0ffset 0x622
  • pause_quanta[15:0] field (bits [15:0]) of the PFC_PAUSE_QUANTA_3 register at 0ffset 0x623
  • pause_quanta[15:0] field (bits [15:0]) of the PFC_PAUSE_QUANTA_4 register at 0ffset 0x624
  • pause_quanta[15:0] field (bits [15:0]) of the PFC_PAUSE_QUANTA_5 register at 0ffset 0x625
  • pause_quanta[15:0] field (bits [15:0]) of the PFC_PAUSE_QUANTA_6 register at 0ffset 0x626
  • pause_quanta[15:0] field (bits [15:0]) of the PFC_PAUSE_QUANTA_7 register at 0ffset 0x627
pfc_pause_quanta_1
pfc_pause_quanta_2
pfc_pause_quanta_3

pfc_pause_quanta_4

pfc_pause_quanta_5
pfc_pause_quanta_6
pfc_pause_quanta_7
remove_pads Selects padding byte removal. If turned on, the IP core strips the padding bytes from the Ethernet packets before sending the data on the RX client interface. If turned off, the IP core maintains the padding bytes and includes them in the data on the RX client interface.
  • Default value is the value you specified for the Remove pads parameter.
  • Value enable: The RX MAC strips the padding bytes from RX packets for which the Length/Type field holds a value smaller than the payload length of the packet. If the packet is a VLAN or Stacked VLAN packet, the IP core reads the Length/Type field in the VLAN or Stacked VLAN header.
  • If RX CRC forwarding is turned on (the parameter editor Keep RX CRC parameter is turned on), you must set the remove_pads parameter to the value of disable.
  • Value disable: The RX MAC does not remove padding bytes from RX packets before sending the data on the RX client interface.

The value of this parameter determines the initial and reset values of the remove_rx_pad field (bit [8]) of the RXMAC_CONTROL register at 0ffset 0x50A.

rx_length_checking Selects whether the IP core checks TX and RX packets for length errors. Length errors include only cases where the payload is shorter than the length indicated in the appropriate Length/Type field.
  • Value enable (default value): The RX MAC indicates an undersized error if the payload size is smaller than the length indicated in the appropriate Length/Type field.
    • If the Length/Type field value is greater than 1500, it does not indicate a length, and the RX MAC does not check the packet for length errors.
    • If the payload is larger than the Length/Type field indicates, the RX MAC does not indicate an error, because the discrepancy could be padding bytes. The IP core accepts over-padded frames.
    • If RX VLAN detection is enabled, the IP core compares the payload length of a VLAN or Stacked VLAN RX packet to the Length/Type field specific to this frame type.
  • Value disable: The RX MAC does not check RX packets for length errors.
  • Despite the rx in the name of this parameter, both the TX MAC and the RX MAC count length errors in the corresponding statistics counters if this parameter has the value of enable and software has not modified the resulting value of 1 in the en_plen field (bit [0]) of the RXMAC_CONTROL register at 0ffset 0x50A.

The value of this parameter determines the initial and reset values of the en_plen field (bit [0]) of the RXMAC_CONTROL register at 0ffset 0x50A.

rx_max_frame_size Sets the maximum packet size (in bytes) the IP core can receive on the Ethernet link without reporting an oversized packet in the RX statistics counters.
  • Default value is the value of the parameter editor RX maximum frame size parameter.
  • Range is 65 through 216–1.
  • If you turn on the Enforce maximum frame size parameter and do not modify the value of the enforce_max_frame_size RTL parameter, or you set the enforce_max_frame_size RTL parameter to enable, the IP core truncates incoming Ethernet packets that exceed this size.

The value of this parameter determines the initial and reset values of the max_rx[15:0] field (bits [15:0]) of the MAX_RX_SIZE_CONFIG register at 0ffset 0x506.

rx_vlan_detection Specifies whether the IP core treats RX VLAN and Stacked VLAN Ethernet frames as regular control frames or detects them and handles them differently.
  • Default value is the value you specify for the parameter editor RX VLAN detection parameter.
  • Value enable: If the parameter has this value, the IP core recognizes RX VLAN and Stacked VLAN Ethernet frames, performs Length/Type field decoding, includes these frame in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the RxFrameOctetsOK counter at offsets 0x962 and 0x963.
  • Value disable: The IP core treats these frames as regular control frames.

The value of this parameter determines the initial and reset values of the disable_rxvlan field (bit [1]) of the RXMAC_CONTROL register at 0ffset 0x50A.

rxcrc_covers_preamble Specifies whether the RX MAC checks CRC under the assumption that it covers the preamble and the standard Ethernet frame (the full Ethernet packet), or only the standard Ethernet frame (without the preamble included in the calculation).
  • Value disable (default value): The RX MAC performs the CRC check assuming a standard Ethernet CRC calculation, which does not include the preamble.
  • Value enable: The RX MAC performs the CRC check assuming the original CRC calculation includes the preamble. This option is useful if preamble passthrough is turned on and the Ethernet link partner also considers the preamble in decoding the CRC.

The value of this parameter determines the initial and reset values of the rxcrc_covers_preamble field (bit [1]) of the RXMAC_EHIP_CFG register at 0ffset 0x50B.

strict_preamble_checking Determines whether the IP core rejects RX packets whose preamble is not the standard Ethernet preamble (0x55_55_55_55_55_55).
  • The default value is the value of the parameter editor Enable strict preamble check parameter.
  • Value enable: The RX MAC drops packets whose preamble (bytes [6:1]) is not the standard Ethernet preamble (0x55_55_55_55_55_55).
  • Value disable: The RX MAC does not examine the preamble bytes of incoming Ethernet packets.
  • This feature is available whether or not you turn on preamble-passthrough. However, the usual reason to turn on preamble-passthrough is to provide a non-standard preamble. In that case strict preamble checking defeats the purpose.
  • This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur.

The value of this parameter determines the initial and reset values of the en_strict_preamble field (bit [4]) of the RXMAC_CONTROL register at 0ffset 0x50A.

strict_sfd_checking Determines whether the IP core rejects RX packets whose SFD byte is not the standard Ethernet SFD (0xD5).
  • The default value is the value of the parameter editor Enable strict SFD check parameter.
  • Value enable: The RX MAC drops packets whose SFD (byte [0]) is not the standard Ethernet SFD (0xD5).
  • Value disable: The RX MAC does not examine the SFD byte of incoming Ethernet packets.
  • This feature is available whether or not you turn on preamble-passthrough.
  • This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur.

The value of this parameter determines the initial and reset values of the en_check_sfd field (bit [3]) of the RXMAC_CONTROL register at 0ffset 0x50A.

tx_ipg_size Specifies the average minimum inter-packet gap (IPG) the IP core maintains on the TX Ethernet link.
  • The default value is the value of the parameter editor Average Inter-packet Gap parameter.
  • Value ipg_12: The TX MAC maintains an average minimum IPG of 12 bytes. This value complies with the Ethernet standard.
  • Value ipg_10: The TX MAC maintains an average minimum IPG of 10 bytes. This non-compliant option increases throughput.
  • Value ipg_8: The TX MAC maintains an average minimum IPG of 8 bytes. This non-compliant option increases throughput further.
  • Value ipg_1: The TX MAC does not attempt to control the minimum IPG. This non-compliant option increases throughput. You can set this value and cede control of the IPG to the application.

The value of this parameter determines the initial and reset values of the ipg[1:0] field (bits [2:1]) of the TXMAC_EHIP_CONFIG register at 0ffset 0x40B.

tx_max_frame_size Sets the maximum packet size (in bytes) the IP core can transmit on the Ethernet link without reporting an oversized packet in the TX statistics counters.
  • Default value is the value of the parameter editor TX maximum frame size parameter.
  • Range is 65 through 216–1.

The value of this parameter determines the initial and reset values of the max_tx[15:0] field (bits [15:0]) of the MAX_TX_SIZE_CONFIG register at 0ffset 0x407.

tx_vlan_detection Specifies whether the IP core treats TX VLAN and Stacked VLAN Ethernet frames as regular control frames or detects them and handles them differently.
  • Default value is the value you specify for the parameter editor TX VLAN detection parameter.
  • Value enable: If the parameter has this value, the IP core recognizes TX VLAN and Stacked VLAN Ethernet frames, performs Length/Type field decoding, includes these frame in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the TxFrameOctetsOK counter at offsets 0x862 and 0x863.
  • Value disable: The IP core treats these frames as regular control frames.

The value of this parameter determines the initial and reset values of the disable_txvlan field (bit [1]) of the TXMAC_CONTROL register at 0ffset 0x40A.

txcrc_covers_preamble Specifies whether the TX MAC generates CRC that covers the preamble and the standard Ethernet frame, or only the standard Ethernet frame
  • Value disable (default value): If i_tx_skip_crc has the value of 0, the TX MAC performs a standard Ethernet CRC calculation, which does not include the preamble, and inserts the result in the outgoing Ethernet frame.
  • Value enable: If i_tx_skip_crc has the value of 0, the TX MAC performs a CRC calculation that includes the preamble, and inserts the result in the outgoing Ethernet frame. This option is useful if preamble passthrough is turned on and the Ethernet link partner also considers the preamble in decoding the CRC.

The value of this parameter determines the initial and reset values of the txcrc_covers_preamble field (bit [9]) of the TXMAC_EHIP_CFG register at 0ffset 0x40B.

uniform_holdoff_quanta Sets the uniform holdoff timer for the TX PFC queues.
  • Default value is 32768.
  • Range is 1 through the largest number of quanta that ensures any PFC XOFF frame the IP core sends will arrive before the previous PFC XOFF frame expires.
  • The value of this parameter, in combination with the values of the individual holdoff timers and flow_control_holdoff_mode (the register fields it affects) determines the frequency with which the TX MAC resends PFC XOFF frames while the corresponding PFC request is asserted.
  • This parameter counts quanta in 100GBASE-R4 variations.

The value of this parameter determines the initial and reset values of the holdoff_all_quanta[15:0] field (bits [15:0]) of the CFG_REATRANSMIT_HOLDOFF_QUANTA register at 0ffset 0x60C.

Related Information
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