Visible to Intel only — GUID: wab1512529004621
Ixiasoft
Visible to Intel only — GUID: wab1512529004621
Ixiasoft
6.2. RX MAC Interface to User Logic
The H-Tile Hard IP for Ethernet IP core RX client interface in MAC+PCS variations employs the Avalon-ST protocol. The Avalon-ST protocol is a synchronous point-to-point, unidirectional interface that connects the producer of a data stream (source) to a consumer of data (sink). The key properties of this interface include:
- Start of packet (SOP) and end of packet (EOP) signals delimit frame transfers.
- The SOP must always be in the MSB, simplifying the interpretation and processing of data you receive on this interface.
- A valid signal qualifies signals from source to sink.
The RX MAC acts as a source and the client acts as a sink in the receive direction.
Name |
Description |
---|---|
i_clk_rx | The RX clock for the IP core is i_clk_rx. The frequency of this clock is 402.832 MHz. |
o_rx_data[511:0] |
RX data. The highest order bit is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order. The IP core reverses the byte order to meet the requirements of the Ethernet standard. If the preamble pass-through feature is enabled, the data begins with the preamble. |
o_rx_valid | When asserted, indicates that RX data is valid. Only valid between the o_rx_startofpacket and o_rx_endofpacket signals. This signal might be deasserted between the assertion of o_rx_startofpacket and o_rx_endofpacket. |
o_rx_empty[5:0] |
Indicates the number of empty bytes on o_rx_data when o_rx_endofpacket is asserted, starting from the least significant byte (LSB). |
o_rx_startofpacket | When asserted, indicates that o_rx_data holds the first clock cycle of data in a packet (start of packet). The IP core asserts this signal for only a single clock cycle for each packet. When o_rx_startofpacket is asserted, the MSB of o_rx_data drives the start of packet. |
o_rx_endofpacket | When asserted, indicates that o_rx_data holds the final clock cycle of data in a packet (end of packet). The IP core asserts this signal for only a single clock cycle for each packet. In the case of an undersized frame or in the case of a frame that is exactly 64 bytes long, o_rx_startofpacket and o_rx_endofpacket might be asserted in the same clock cycle. |
o_rx_error[5:0] | Reports certain types of errors in the Ethernet frame whose contents are currently being transmitted on the client interface. This signal is valid in EOP cycles only. The individual bits report different types of errors:
|
o_rxstatus_valid | When asserted, indicates that o_rxstatus_data is driving valid data. |
o_rxstatus_data[39:0] | Specifies information about the received frame. The following fields are defined:
|
o_rx_pause | When asserted, indicates the IP core received a PAUSE XOFF frame on the Ethernet link. The IP core deasserts this signal when the quanta count from the PAUSE XOFF request expires. If you set the parameter editor Stop TX traffic when link partner sends pause parameter to the value of Yes, or overwrite it with the sfc or both value for the flow_control RTL parameter, the TX MAC stops traffic in response to the PAUSE XOFF frame. In this case, the quanta count decrements while the IP core stops traffic. If the settings direct the TX MAC to not stop traffic in response to the PAUSE XOFF frame, the quanta counter decrements on every valid cycle on the TX MAC client interface. Each quanta represents 512 bits. Therefore, the counter decrements by one half in every valid clock cycle. |
o_rx_pfc[7:0] | When a bit is asserted, indicates the IP core received a PFC XOFF frame on the Ethernet link for the corresponding priority queue. The IP core deasserts each bit when the XOFF frame's quanta count expires. The PFC quanta counters decrement on every valid cycle on the TX MAC client interface. Each quanta represents 512 bits. Therefore, the counter decrements by one half in every valid clock cycle. In summary, the width of the pulse indicates the length of the requested pause in traffic for the queue. |