H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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ID 683430
Date 5/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the H-Tile Hard IP for Ethernet IP Core 2. Getting Started 3. H-Tile Hard IP for Ethernet Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Ethernet Toolkit Overview 8. H-Tile Hard IP for Ethernet IP User Guide Archives 9. Document Revision History for the H-Tile Hard IP for Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices A. Advanced RTL Parameters B. Ethernet Reconfiguration and Status Register Descriptions
1. About the H-Tile Hard IP for Ethernet IP Core x
1.1. IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. H-Tile Hard IP for Ethernet IP Core Device Family Support 1.2.2. H-Tile Hard IP for Ethernet IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design 2.5. IP Core Testbenches 2.6. Compiling the Full Design and Programming the FPGA
2.4. Integrating Your IP Core in Your Design x
2.4.1. Channel Placement 2.4.2. Pin Assignments 2.4.3. Adding the Transceiver PLLs 2.4.4. Clock Requirements 2.4.5. Placement Settings for the H-Tile Hard IP for Ethernet IP Core
2.4.4. Clock Requirements x
2.4.4.1. Clock Connection Requirements
3. H-Tile Hard IP for Ethernet Parameters x
3.1. Parameter Editor Parameters 3.2. RTL Parameters
4. Functional Description x
4.1. High Level System Overview 4.2. H-Tile Hard IP for Ethernet IP Core MAC Interface 4.3. H-Tile Hard IP for Ethernet IP PCS Only/PCS66 Interface 4.4. Auto-Negotiation and Link Training
4.2. H-Tile Hard IP for Ethernet IP Core MAC Interface x
4.2.1. H-Tile Hard IP for Ethernet IP Core TX Datapath 4.2.2. H-Tile Hard IP for Ethernet IP Core RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Pause Control and Generation Interface 4.2.5. Pause Control Frame Filtering 4.2.6. Link Fault Signaling 4.2.7. Statistics Counters Interface 4.2.8. Order of Ethernet Transmission
4.2.1. H-Tile Hard IP for Ethernet IP Core TX Datapath x
4.2.1.1. Preamble, Start, and SFD Insertion 4.2.1.2. Length/Type Field Processing 4.2.1.3. Frame Padding 4.2.1.4. Frame Check Sequence (CRC-32) Insertion 4.2.1.5. Inter-Packet Gap Generation and Insertion
4.2.2. H-Tile Hard IP for Ethernet IP Core RX Datapath x
4.2.2.1. H-Tile Hard IP for Ethernet IP Core RX Filtering 4.2.2.2. H-Tile Hard IP for Ethernet IP Core Preamble Processing 4.2.2.3. IP Core Strict SFD Checking 4.2.2.4. RX FCS Checking 4.2.2.5. RX Malformed Packet Handling 4.2.2.6. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.7. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.8. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission
4.2.7. Statistics Counters Interface x
4.2.7.1. Statistic Counters Rollover Limitations
4.3. H-Tile Hard IP for Ethernet IP PCS Only/PCS66 Interface x
4.3.1. TX PCS and RX PCS Datapath
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. TX PCS Interface to User Logic 6.4. RX PCS Interface to User Logic 6.5. FlexE and OTN Mode TX Interface 6.6. FlexE and OTN Mode RX Interface 6.7. Ethernet Link and Transceiver Signals 6.8. Transceiver Reconfiguration Signals 6.9. Ethernet Reconfiguration Interface 6.10. Miscellaneous Status and Debug Signals 6.11. Reset Signals 6.12. Clocks
6.8. Transceiver Reconfiguration Signals x
6.8.1. Disabling Background Calibration
7. Ethernet Toolkit Overview x
7.1. Features
B. Ethernet Reconfiguration and Status Register Descriptions x
B.1. Auto-Negotiation and Link Training Registers B.2. PHY Registers B.3. TX MAC Registers B.4. RX MAC Registers B.5. Pause and Priority- Based Flow Control Registers B.6. TX Statistics Counter Registers B.7. RX Statistics Counter Registers
B.1. Auto-Negotiation and Link Training Registers x
B.1.1. ANLT Sequencer Config B.1.2. ANLT Sequencer Status B.1.3. Auto-Negotiation Config Register 1 Auto-Negotiation Config Register 1 Fields B.1.4. Auto-Negotiation Config Register 2 B.1.5. Auto-Negotiation Status Register B.1.6. Auto Negotiation Config Register 3 B.1.7. Auto-Negotiation Config Register 4 B.1.8. Auto-Negotiation Config Register 5 B.1.9. Auto-Negotiation Config Register 6 B.1.10. Auto-Negotiation Status Register 1 B.1.11. Auto-Negotiation Status Register 2 B.1.12. Auto-Negotiation Status Register 3 B.1.13. Auto-Negotiation Status Register 4 B.1.14. Auto-Negotiation Status Register 5 B.1.15. Consortium Next Page Override B.1.16. Consortium Next Page Link Partner Status B.1.17. Link Training Config Register 1 B.1.18. Link Training Config Register 2 B.1.19. Link Training Status Register 1 B.1.20. Link Training Config Register for Lane 0 B.1.21. Link Training Frame Contents for Lane 0 B.1.22. Local Transceiver TX EQ 1 Settings for Lane 0 B.1.23. Local Transceiver TX EQ 2 Settings for Lane 0 B.1.24. Local Link Training Parameters B.1.25. Link Training Config Register for Lane 1 B.1.26. Link Training Frame Contents for Lane 1 B.1.27. Local Transceiver TX EQ 1 Settings for Lane 1 B.1.28. Local Transceiver TX EQ 2 Settings for Lane 1 B.1.29. Link Training Config Register for Lane 2 B.1.30. Link Training Frame Contents for Lane 2 B.1.31. Local Transceiver TX EQ 1 Settings for Lane 2 B.1.32. Local Transceiver TX EQ 2 Settings for Lane 2 B.1.33. Link Training Config Register for Lane 3 B.1.34. Link Training Frame Contents for Lane 3 B.1.35. Local Transceiver TX EQ 1 Settings for Lane 3 B.1.36. Local Transceiver TX EQ 2 Settings for Lane 3
B.2. PHY Registers x
B.2.1. PHY Module Revision ID B.2.2. PHY Scratch Register B.2.3. PHY Configuration B.2.4. PMA Serial Loopback B.2.5. TX PLL Locked B.2.6. RX CDR PLL Locked B.2.7. TX Datapath Ready B.2.8. Frame Errors Detected B.2.9. Clear Frame Errors B.2.10. Reset Registers B.2.11. RX PCS Status for AN/LT B.2.12. PCS Error Injection B.2.13. Alignment Marker Lock B.2.14. BER Count B.2.15. PCS Virtual Lane 0 B.2.16. PCS Virtual Lane 1 B.2.17. PCS Virtual Lane 2 B.2.18. PCS Virtual Lane 3 B.2.19. Recovered Clock Frequency in KHz B.2.20. TX Clock Frequency in KHz
B.3. TX MAC Registers x
B.3.1. TX MAC Module Revision ID B.3.2. TX MAC Scratch Register B.3.3. Reserved B.3.4. Link Fault Configuration B.3.5. IPG Words to remove per Alignment Marker Period B.3.6. Maximum TX Frame Size B.3.7. TX MAC Configuration B.3.8. EHIP TX MAC Feature Configuration B.3.9. TX MAC Source Address Lower Bytes B.3.10. TX MAC Source Address Higher Bytes
B.4. RX MAC Registers x
B.4.1. RX MAC Module Revision ID B.4.2. RX MAC Scratch Register B.4.3. Reserved B.4.4. Maximum RX Frame Size B.4.5. RX CRC Forwarding B.4.6. Link Fault Status B.4.7. RX MAC Configuration B.4.8. EHIP RX MAC Feature Configuration
B.5. Pause and Priority- Based Flow Control Registers x
B.5.1. TXSFC Module Revision ID B.5.2. TX SFC Scratch Register B.5.3. Reserved B.5.4. Enable TX Pause Ports B.5.5. TX Pause Request B.5.6. Enable Automatic TX Pause Retransmission B.5.7. Retransmit Holdoff Quanta B.5.8. Retransmit Pause Quanta B.5.9. Enable TX XOFF B.5.10. Enable Uniform Holdoff B.5.11. Set Uniform Holdoff B.5.12. Lower 4 bytes of the Destination address for Flow Control B.5.13. Higher 2 bytes of the Destination address for Flow Control B.5.14. Lower 4 bytes of the Source address for Flow Control frames B.5.15. Higher 2 bytes of the Source address for Flow Control frames B.5.16. TX Flow Control Feature Configuration B.5.17. Pause Quanta 0 B.5.18. Pause Quanta 1 B.5.19. Pause Quanta 2 B.5.20. Pause Quanta 3 B.5.21. Pause Quanta 4 B.5.22. Pause Quanta 5 B.5.23. Pause Quanta 6 B.5.24. Pause Quanta 7 B.5.25. PFC Holdoff Quanta 0 B.5.26. PFC Holdoff Quanta 1 B.5.27. PFC Holdoff Quanta 2 B.5.28. PFC Holdoff Quanta 3 B.5.29. PFC Holdoff Quanta 4 B.5.30. PFC Holdoff Quanta 5 B.5.31. PFC Holdoff Quanta 6 B.5.32. PFC Holdoff Quanta 7 B.5.33. RXSFC Module Revision ID B.5.34. RXSFC Scratch Register B.5.35. Reserved B.5.36. Enable RX Pause Frame Processing B.5.37. Forward Flow Control Frames B.5.38. Lower 4 bytes of the Destination address for RX Pause Frames B.5.39. Higher 2 bytes of the Destination address for RX Pause Frames
B.6. TX Statistics Counter Registers x
B.6.1. TX Frames less than 64 bytes with CRC error (lower 32 bits) B.6.2. TX Frames less than 64 bytes with CRC error (upper 32 bits) B.6.3. Oversized TX frames with CRC error (lower 32 bits) B.6.4. Oversized TX frames with CRC error (upper 32 bits) B.6.5. TX Frames of any size with a CRC error (lower 32 bits) B.6.6. TX Frames of any size with a CRC error (upper 32 bits) B.6.7. TX Frames of any size with a CRC error on OK packet (lower 32 bits) B.6.8. TX Frames of any size with a CRC error on OK packet (upper 32 bits) B.6.9. Multicast TX data frames with CRC error (lower 32 bits) B.6.10. Multicast TX data frames with CRC error (upper 32 bits) B.6.11. Broadcast TX data frames with CRC error (lower 32 bits) B.6.12. Broadcast TX data frames with CRC error (upper 32 bits) B.6.13. Unicast TX data frames with CRC error (lower 32 bits) B.6.14. Unicast TX data frames with CRC error (upper 32 bits) B.6.15. Multicast TX control frames with CRC error (lower 32 bits) B.6.16. Multicast TX control frames with CRC error (upper 32 bits) B.6.17. Broadcast TX control frames with CRC error (lower 32 bits) B.6.18. Broadcast TX control frames with CRC error (upper 32 bits) B.6.19. Unicast TX control frames with CRC error (lower 32 bits) B.6.20. Unicast TX control frames with CRC error (upper 32 bits) B.6.21. TX Pause frame with CRC error (lower 32 bits) B.6.22. TX Pause frame with CRC error (upper 32 bits) B.6.23. 64 byte TX frames (lower 32 bits) B.6.24. 64 byte TX frames (upper 32 bits) B.6.25. 65 to 127 byte TX frames (lower 32 bits) B.6.26. 65 to 127 byte TX frames (upper 32 bits) B.6.27. 128 to 257 byte TX frames (lower 32 bits) B.6.28. 128 to 257 byte TX frames (upper 32 bits) B.6.29. 256 to 511 byte TX frames (lower 32 bits) B.6.30. 256 to 511 byte TX frames (upper 32 bits) B.6.31. 512 to 1023 byte TX frames (lower 32 bits) B.6.32. 512 to 1023 byte TX frames (upper 32 bits) B.6.33. 1024 to 1518 byte TX frames (lower 32 bits) B.6.34. 1024 to 1518 byte TX frames (upper 32 bits) B.6.35. 1519 to max size TX frames (lower 32 bits) B.6.36. 1519 to max size TX frames (upper 32 bits) B.6.37. Oversize TX frames (lower 32 bits) B.6.38. Oversize TX frames (upper 32 bits) B.6.39. Multicast TX data frames without error (lower 32 bits) B.6.40. Multicast TX data frames without error (upper 32 bits) B.6.41. Broadcast TX data frames without error (lower 32 bits) B.6.42. Broadcast TX data frames without error (upper 32 bits) B.6.43. Unicast TX data frames without error (lower 32 bits) B.6.44. Unicast TX data frames without error (upper 32 bits) B.6.45. Multicast TX control frames without error (lower 32 bits) B.6.46. Multicast TX control frames without error (upper 32 bits) B.6.47. Broadcast TX control frames without error (lower 32 bits) B.6.48. Broadcast TX control frames without error (upper 32 bits) B.6.49. Unicast TX control frames without error (lower 32 bits) B.6.50. Unicast TX control frames without error (upper 32 bits) B.6.51. TX Pause frames without error (lower 32 bits) B.6.52. TX Pause frames without error (upper 32 bits) B.6.53. TX Frames with less than 64 bytes and a CRC error (lower 32 bits) B.6.54. TX Frames with less than 64 bytes and a CRC error (upper 32 bits) B.6.55. Number of TX frame starts (lower 32 bits) B.6.56. Number of TX frame starts (upper 32 bits) B.6.57. Number of TX length errors (lower 32 bits) B.6.58. Number of TX length errors (upper 32 bits) B.6.59. TX PFC frame with CRC error (lower 32 bits) B.6.60. TX PFC frame with CRC error (upper 32 bits) B.6.61. TX PFC frames without error (lower 32 bits) B.6.62. TX PFC frames without error (upper 32 bits) B.6.63. TXSTAT Module Revision ID B.6.64. TXSTAT Scratch Register B.6.65. Reserved B.6.66. Configure TX Statistics Counters B.6.67. TX Statistics Counter Status B.6.68. TX Payload bytes with no errors (lower 32 bits) B.6.69. TX Payload bytes with no errors (upper 32 bits) B.6.70. TX Frame bytes with no errors (lower 32 bits) B.6.71. TX Frame bytes with no errors (upper 32 bits) B.6.72. TX Malformed frames (lower 32 bits) B.6.73. TX Malformed frames (upper 32 bits) B.6.74. TX Packets that were dropped due to error (lower 32 bits) B.6.75. TX Packets that were dropped due to error (upper 32 bits) B.6.76. TX Frames with bad length/type field (lower 32 bits) B.6.77. TX Frames with bad length/type field (upper 32 bits)
B.7. RX Statistics Counter Registers x
B.7.1. RX Frames less than 64 bytes with CRC error (lower 32 bits) B.7.2. RX Frames less than 64 bytes with CRC error (upper 32 bits) B.7.3. Oversized RX frames with CRC error (lower 32 bits) B.7.4. Oversized RX frames with CRC error (upper 32 bits) B.7.5. RX Frames of any size with a CRC error (lower 32 bits) B.7.6. RX Frames of any size with a CRC error (upper 32 bits) B.7.7. RX Frames of any size with a CRC error on OK packet (lower 32 bits) B.7.8. RX Frames of any size with a CRC error on OK packet (upper 32 bits) B.7.9. Multicast RX data frames with CRC error (lower 32 bits) B.7.10. Multicast RX data frames with CRC error (upper 32 bits) B.7.11. Broadcast RX data frames with CRC error (lower 32 bits) B.7.12. Broadcast RX data frames with CRC error (upper 32 bits) B.7.13. Unicast RX data frames with CRC error (lower 32 bits) B.7.14. Unicast RX data frames with CRC error (upper 32 bits) B.7.15. Multicast RX control frames with CRC error (lower 32 bits) B.7.16. Multicast RX control frames with CRC error (upper 32 bits) B.7.17. Broadcast RX control frames with CRC error (lower 32 bits) B.7.18. Broadcast RX control frames with CRC error (upper 32 bits) B.7.19. Unicast RX control frames with CRC error (lower 32 bits) B.7.20. Unicast RX control frames with CRC error (upper 32 bits) B.7.21. RX Pause frame with CRC error (lower 32 bits) B.7.22. RX Pause frame with CRC error (upper 32 bits) B.7.23. 64 byte RX frames (lower 32 bits) B.7.24. 64 byte RX frames (upper 32 bits) B.7.25. 65 to 127 byte RX frames (lower 32 bits) B.7.26. 65 to 127 byte RX frames (upper 32 bits) B.7.27. 128 to 257 byte RX frames (lower 32 bits) B.7.28. 128 to 257 byte RX frames (upper 32 bits) B.7.29. 256 to 511 byte RX frames (lower 32 bits) B.7.30. 256 to 511 byte RX frames (upper 32 bits) B.7.31. 512 to 1023 byte RX frames (lower 32 bits) B.7.32. 512 to 1023 byte RX frames (upper 32 bits) B.7.33. 1024 to 1518 byte RX frames (lower 32 bits) B.7.34. 1024 to 1518 byte RX frames (upper 32 bits) B.7.35. 1519 to max size RX frames (lower 32 bits) B.7.36. 1519 to max size RX frames (upper 32 bits) B.7.37. Oversize RX frames (lower 32 bits) B.7.38. Oversize RX frames (upper 32 bits) B.7.39. Multicast RX data frames without error (lower 32 bits) B.7.40. Multicast RX data frames without error (upper 32 bits) B.7.41. Broadcast RX data frames without error (lower 32 bits) B.7.42. Broadcast RX data frames without error (upper 32 bits) B.7.43. Unicast RX data frames without error (lower 32 bits) B.7.44. Unicast RX data frames without error (upper 32 bits) B.7.45. Multicast RX control frames without error (lower 32 bits) B.7.46. Multicast RX control frames without error (upper 32 bits) B.7.47. Broadcast RX control frames without error (lower 32 bits) B.7.48. Broadcast RX control frames without error (upper 32 bits) B.7.49. Unicast RX control frames without error (lower 32 bits) B.7.50. Unicast RX control frames without error (upper 32 bits) B.7.51. RX Pause frames without error (lower 32 bits) B.7.52. RX Pause frames without error (upper 32 bits) B.7.53. RX Frames with less than 64 bytes and a CRC error (lower 32 bits) B.7.54. RX Frames with less than 64 bytes and a CRC error (upper 32 bits) B.7.55. Number of RX frame starts (lower 32 bits) B.7.56. Number of RX frame starts (upper 32 bits) B.7.57. Number of RX length errors (lower 32 bits) B.7.58. Number of RX length errors (upper 32 bits) B.7.59. RX PFC frame with CRC error (lower 32 bits) B.7.60. RX PFC frame with CRC error (upper 32 bits) B.7.61. RX PFC frames without error (lower 32 bits) B.7.62. RX PFC frames without error (upper 32 bits) B.7.63. RXSTAT Module Revision ID B.7.64. RXSTAT Scratch Register B.7.65. Reserved B.7.66. Reserved B.7.67. Reserved B.7.68. Configure RX Statistics Counters B.7.69. RX Statistics Counter Status B.7.70. RX Payload bytes with no errors (lower 32 bits) B.7.71. RX Payload bytes with no errors (upper 32 bits) B.7.72. RX Frame bytes with no errors (lower 32 bits) B.7.73. RX Frame bytes with no errors (upper 32 bits) B.7.74. RX Malformed frames (lower 32 bits) B.7.75. RX Malformed frames (upper 32 bits) B.7.76. RX Packets that were dropped due to error (lower 32 bits) B.7.77. RX Packets that were dropped due to error (upper 32 bits) B.7.78. RX Frames with bad length/type field (lower 32 bits) B.7.79. RX Frames with bad length/type field (upper 32 bits)
1. About the H-Tile Hard IP for Ethernet IP Core
2. Getting Started
3. H-Tile Hard IP for Ethernet Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Ethernet Toolkit Overview
8. H-Tile Hard IP for Ethernet IP User Guide Archives
9. Document Revision History for the H-Tile Hard IP for Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices
A. Advanced RTL Parameters
B. Ethernet Reconfiguration and Status Register Descriptions

B.1.3. Auto-Negotiation Config Register 1

Provides the following configuration options:
  • Enable Auto-negotiation
  • Enable User controlled base pages
  • Enable User controlled next pages
  • Local device remote fault
  • Force TX nonce value
  • Override Auto-negotiation parameters
  • Ignore Nonce field
  • Enable Consortium Next Page Send
  • Enable Consortium Next Page Receive
  • Enable Consortium Next Page Override
  • Ignore Consortium Next Page Tech Ability Code

Offset: 0xC0

Access: RW

Auto-Negotiation Config Register 1 Fields

Bit Name Description Access Reset
11 ignore_consortium_next_page_tech_ability_code Ignore Consortium NextPage Tech Ability Code

1: AN function will accept any unformatted Next Page after a formatted next page tagged with the proper OUI for resolving Consortium AN modes

0: The AN function will only accept an unformatted Next Page with the code 0x003 in bits D8:D0 of the page to resolve Consortium AN modes

RW 0x0
10 enable_consortium_next_page_override Enable Consortium Next Page override

1: Data sent to the consortium next page will come from a Consortium Override Register instead of being set automatically

0: Normal operation

RW 0x0
9 enable_consortium_next_page_receive Enable Consortium Next Page receive

1: Enable decoding received Consortium Next Pages to resolve auto-negotiation

0: Normal operation

  • If this feature is disabled, Next pages will be ignored for the purpose of resolving auto-negotiation
 RW 0x1
8 enable_consortium_next_page_send Enable Consortium Next Page send

1: Send Consortium next pages immediately after the base page

0: Normal operation

  • This feature defaults to 0 for 100GBASE-R4
  • If this feature is enabled while User Next Pages are enabled, the Consortium pages will replace the first 2 User defined pages
RW 0x0
7 ignore_nonce_field Ignore Nonce Field

1: Ignore the Nonce field during AN

0: Normal operation

  • AN will normally fail in loopback due to the Nonce field
  • To use AN with loopback, disable Nonce bit checking using this feature
  • In simulation, the default value is 1. In synthesis, the default value is 0.
RW 0x0
5 override_an_parameters_enable Override AN Parameters

1: Use the bits from parameter override CSRs to compose the default base page

0: Normal operation

 RW 0x0
4 force_tx_nonce_value Force TX Nonce value

1: Force the TX Nonce value to support UNH testing

0: Normal operation 		RW 0x0
3 local_device_remote_fault Force Local device remote fault

1: Signal a remote fault using appropriate bit in the AN pages

0: Normal operation

 RW 0x0
2 an_next_pages_ctrl Enable User Controlled AN Next Pages

1: User controlled next pages are enabled; the User Next page CSRs control the next page use for AN

0: The AN logic will automatically generate next pages based on the Ethernet Core Variant and its parameters

  • Enable this feature if you need to control the content of the AN Next page
  • Leave this feature disabled if you want the core to perform default negotiation for its type
RW 0x0
1 an_base_pages_ctrl Enable User Controlled AN Base Pages

1: User controlled base pages are enabled; the User Base page CSRs control the base page used for AN

0: The AN logic will automatically generate base pages based on the Ethernet Core Variant and its parameters

  • Enable this feature if you need to control the content of the AN Base page
  • Leave this feature disabled if you want the core to perform default negotiation for its type
RW 0x0
0 enable_an Enable Auto-Negotiation

1: Enable Auto-negotiation (default)

0: Disable Auto-negotiation

  • Equivalent to state variable mr_autoneg_enable in IEEE 802.3 CL73.10.1
 RW 0x1
Level Two Title